Design of a DVB-S2 compliant LDPC decoder for FPGA

Abstract

Low Density Parity Check codes presents itself as the dominant FEC code in terms of performance, having the nearest performance to the Shannon limit and proving its usefulness in the increasing range of applications and standards that already used it. Low power devices are not except of this rapid development, where it emerges the necessity of decoders of low power without totally sacrificing performance or resource usage. The present work details research for a LDPC decoder compliant with the DVB-S2 standard for digital television, motivated for its already established use in uplink and downlink satellite applications and its great performance at large code lengths. Specifically, this research presents the study of the min-sum algorithm and the elements that conform the core decoder, including both functional units (variable and check nodes), memory blocks and routing network. In the context of DVB-S2, it is focused in the inner LDPC decoder and targets FPGA as platform. Furthermore, a variety of design strategies are considered as part of the scope of this work, including the optimal selection of the architecture and the schedule policy, the basis of the design characteristics of the control unit as a Algorithmic State Machine and the introduction of specialized modules to reduce the number of clock cycles per decoding process, such as early stopping. Under these constrains, it has been selected a set of features for a core design derived from work, such as code length of 64800 bits and code rate equal to 1/2. The proposed architecture is partially parallel with flooding schedule and operation over binary symbols (Galois field GF(2)). It takes the assumption of a channel with AWGN and BPSK modulation, so the demodulator feeds soft decision information of each symbol based on both assumptions.