ANEXO I ANEXO 1.1 Sistemas Automáticos de Medición de Volúmenes a. Sistema de captura de datos de paquetes estáticos comerciales DM3500-IR El DM3500 [5] es una unidad compacta de dimensionamiento que mide automáticamente la longitud, el ancho y altura de paquetes a medida que se transportan sobre una cinta transportadora a través de la superficie de lectura de código de barras. La unidad de dimensionamiento autónoma está diseñada para la instalación simple a través de los sistemas de transporte existentes. En la figura 1.3 se observa la máquina de medición descrita.  Exactitud: 0.25cm (altura), 0.51cm (ancho y largo)  Velocidad de faja: 0.61m/s  Rango de medición: 152.4cm (ancho), 373.38cm (largo) y 91cm (alto).  Tecnología: arreglo de cámaras CCD y diodos laser  Orientación: No es necesario orientar el objeto  Interface: RS232 y Ethernet (TCP/IP)  Tipo de sistema: dinámico Fig.1.3. Dispositivo de mediciónDM3500-IR de ACCU-Sort System. Página | 1 CSN910 FlexFlow™ La figura 1.4 muestra este dispositivo que representa una alternativa de solución para la captura de datos no atendida que escanea la identificación y mide las dimensiones de paquetes que se desplazan sobre un transportador. Posee una velocidad de medición y capacidad de procesamiento adecuadas, control total del contaje de paquetes y una correcta clasificación y manipulación del material durante de todo el proceso [6].  Exactitud: 2mm (altura), 5mm (ancho y largo)  Velocidad de faja: 3m/s  Rango de medición: 120cm (ancho), 2500cm (largo) y 700cm (alto).  Tecnología: laser Fig.1.4. Máquina de medición  Rendimiento: 15000 objetos por hora CS910 FlexFlow de Metler  Interface: RS232 y Ethernet (TCP/IP) Toledo.  Orientación: No es necesario orientar el objeto  Tipo de sistema: dinámico TLX MultiCapture™ Es una solución global de captura de datos en movimiento diseñada para su integración en los sistemas de cinta transportadora de manipulación de paquetes guiada o no guiada. Los paquetes son separados automáticamente si la distancia entre ellos no garantiza la medición, pesaje e identificación de los mismos. El sistema está disponible en dos versiones; una totalmente automática y otra con opción de validación donde el operario puede introducir los datos que faltan del paquete [7], La figura 1.5 ilustra el sistema de medición descrito Fig.1.5. Dispositivo de medición TLX MultiCapture. Página | 2 Entre sus especificaciones tenemos: - Precisión: +/-2 mm altura +/- 5mm anchura y longitud - Tamaño máx. del objeto: 1200 x 900 x 900 mm - Tamaño mín. del objeto: 150 x 50 x 25 mm - Rendimiento: 90 m/min CSN210 MassFlow™ Es un sistema de vigilancia para adquirir automáticamente las dimensiones y la identificación de las mercancías movilizadas en un transportador. El haz de luz paralelo explora sobre cada elemento, captando todos los detalles, sin riesgo de sombreado. El diseño es modular, por ende, significa que el sistema se puede integrar completamente con escalas en movimiento y lectores de código de barras para adaptarse a las aplicaciones más exigentes de manipulación de embalaje [8]. Una ilustración del sistema Fig.1.6.Sistema de Medición se observa en la figura 1.6. CSN210 MassFlow Entre sus especificaciones tenemos: - Precisión: ± 5 mm - Tamaño máx. del objeto: 3000 x 1800 x 920 mm - Tamaño mín. del objeto: 50 x 50 x 25 mm - Velocidad de la faja: 1.3 m/s [14] Página | 3 CubiScan 200TS La ventaja más representativa de este dispositivo es la integración en movimiento, dimensionamiento y sistema de pesaje para maximizar el rendimiento y la eficiencia de los procesos de la industria. Usa tecnología de luz infrarroja, una representación gráfica de esta máquina se observa en la figura 1.7 [9].  Exactitud: 5mm  Velocidad de faja: 0.5m/s a 1.16m/s  Rango de medición: 153cm (largo), 122cm (ancho) y 92cm (alto).  Tecnología: sensores infrarrojos.  Interface: RS232.  Orientación: No es necesario orientar el objeto.  Tipo de sistema: Dinámico Fig. 1.7. Dispositivo de medición CubiScan200TS b. Sistema de captura de datos de paquetes estáticos comerciales ExpressCube 265R La capacidad de medición y pesaje de este sistema la hace ideal para el comercio electrónico y aplicaciones de transporte de carga. La figura 1.8 brinda una representación gráfica de tal dispositivo [10].  Exactitud: 5mm  Rango de medición: 60cm (largo), 65.5m (ancho) y 94cm (alto).  Peso máximo: 70kg  Interface: RS232 y USB  Tipo de sistema: estático Fig. 1.8. Dispositivo de medición ExpressCube 265R Página | 4 CSN810 TableTop™ Está diseñado para medir las dimensiones de objetos rectangulares colocados sobre una superficie nivelada. Se monta en alto y ahorra, así, espacio en el suelo; exige poca reorganización, o ninguna en absoluto, de las operaciones existentes y permite moverse sin impedimentos por debajo de él. En la figura 1.9 se observa el dispositivo descrito [11] Entre sus especificaciones tenemos las siguientes: - Precisión: ±5mm - Tamaño máx. del objeto: 1200mm x 900mm x 900mm - Tamaño mín. del objeto: 50mm x 50mm x 50mm Fig.1.9. Máquina de medición CSN810 TableTop ANEXO 1.2 Variables Inmersas en la Operación de los Sistemas Automáticos de Medición de Volúmenes. 1.2.1. Variables Externas. La figura 1.10 muestra las variables externas que ejercen influencia y son afectadas por el desarrollo del sistema de medición, tanto en el nivel organizacional, especifico y general. Página | 5 Fig. 1.10. Variables Externas que afectan el desarrollo del sistema a implementarse. Página | 6 1.2.2. Variables Internas El diagrama de flujo de los procesos de almacenamiento, empaquetamiento y transporte de productos se muestra en la figura 1.11, donde además se señalan las variables internas que afectan sus desarrollos. Asimismo la tabla 1.1 brinda mejor información y explicación de cómo las variables internas identificadas anteriormente ejercen influencia en ciertas actividades de los procesos mencionados en el párrafo anterior. Página | 7 Inicio Recibimiento o 1) Falta o creación de desperdicio de productos PROCESO DE ALMACENAMIENTO materiales Y COMERCIO DE BIENES Compra de materiales para empaquetamiento o 2) Perdida de tiempo almacenamiento en el desarrollo del (Cajas) proceso Busqueda de cajas según el mateial 3) Falta de mejor control para Hacer pedido de la verificación del estado de las materiales cajas ¿Cajas en buen estado? No 4) Sobrecarga de trabajo para los Sí operarios Fig. 1.11. Variables internas Empaquetamiento o que intervienen en el 5) Inadecuado control almacenamiento para la estimación del desarrollo del sistema. numero de cajas a utilizar ¿Numero No q suficiente de cajas? Sí 6) Falta de control Transporte de Carga para el adecuado y eficiente transporte No de carga y su costo No ¿Hay presupuesto ¿Suficientes para contratar mas unidades? unidades? 7) Incremento del impacto sobre el medio ambiente por la actividad industrial Sí Sí Contratar mas unidades No 8) Falta de un adecuado Comercio ¿Almacenamiento? control para la correcta estimación de la cantidad Sí de espacio y dinero a utilizar No ¿Hay presupuesto ¿Suficiente espacio para para alquilar mas almacenar los bienes? lugares? No Sí Sí Almacen Alquilar o comprar mas lugares Fin Tabla 1.1. Descripción de los problemas originados por variables internas. Página | 8 HECHOS PROBLEMAS Y CAUSAS La falta de un adecuado sistema de control para el dimensionamiento de los 1) Falta o desperdicio de materiales. productos y la cantidad de ellos, produce un aumento en el costo de compre de materiales y pérdida de tiempo en el flujo de procesos de la empresa. En el proceso de empaquetamiento de los productos, los operarios pierden 2) Pérdida de tiempo en el desarrollo del mucho tiempo buscando las cajas adecuadas para ellos, más aun si lo hacen proceso. sin alguna clasificación anterior, lo que genera retraso e interrupción en el desarrollo del proceso. Sin un sistema de monitoreo de las dimensiones de los cajas, los productos 3) Falta de control para verificar el estado serán mal empaquetados y pueden ser dañados, originando baja calidad de de las cajas. éste ante los compradores. La búsqueda de los empaques adecuados para cada producto, el deterioro o falta de ellos será verificado por los trabajadores de manera directa, lo que 4) Sobrecarga de trabajo para los produce sobrecarga en su labor, aumento de las jornadas, que se vuelven operarios. arduas y rutinarias. Esto, a su vez, causa estrés y fatiga en los operarios, lo que constituirá en la disminución de la productividad de la empresa. Ineficiente control para el cálculo de las cajas a utilizar significará el aumento de 5) Inadecuado control para la estimación costo del material y mano de obra, así como retardo en el desarrollo del del número de cajas a utilizar. proceso. Sin la implementación de un sistema de medición y peso de los productos, 6) Falta de control para el adecuado y originará perdidas en la economía de la empresa, por la contratación de nuevas eficiente transporte de la carga y su unidades para cumplir con el requerimiento, o la interrupción del flujo del costo. proceso si no hay unidades de transporte El aumento de las unidades de transporte causara incremento de 7) Incremento del impacto sobre el medio contaminación del medio ambiente, por la liberación de gases, combustión, ambiente por la actividad industrial. ruido, etc. 8) Falta de un adecuado control para la La falta de implementación de un sistema de medición originara en ineficiente correcta estimación de la cantidad de uso de los espacios asignados para el almacenamiento e incremento de costos espacio y dinero a utilizar. por la compra o alquiler de nuevas zonas. Fuente: Elaboración propia Página | 9 ANEXO Nº2: MARCAS COMERCIALES DE SENSORES A UTILIZAR Sensor ultrasónico: U-GAGE™ S18U Banner Engineering  Rango de censado: 30 a 300 mm  Tiempo de respuestas: 2.5ms o 30 ms  Salida: 4-20mA  Alimentación: 10 a 30V dc - 65mA máx.  Frecuencia ultrasónica: 300 kHz.  Resolución: 1mm Figura A.7. Sensores ultrasónicos Diodo Infrarrojo GP2Y0A21YK0F: Sharp  Medición de distancias  Rango de censado: 10 a 80 cm  Alimentación: 4.5 a 5.5v – 30mA máx.  Salida: 0.5v a 2.25v no lineal  Tiempo de respuesta: 50ms Figura A.8. Sensor infrarrojo. Sensor Fotoeléctrico: Q12AB6FF50 Banner Engineering  Modo operación: difuso  Lógica: PNP o NPN (detector de presencia)  Rango de censado: hasta 50 mm  Diámetro del haz de luz: 0.5 mm @ 16 mm  Alimentación: 10 a 30V dc 20Ma máx.  Tiempo de respuestas: 700us Figura A.9. Sensor fotoeléctrico. Página | 10 Sensor Óptico Modelo GP2Y0D810Z0F SHARP  Utiliza un diodo emisor infrarrojo y un fotodiodo.  Voltaje de alimentación: 2.7 a 6.2V.  Rango de detección: 80 a 130mm.  Voltaje de salida digital: nivel bajo 0.6V como máximo y nivel alto igual al voltaje de alimentación menos 0.6V como mínimo.  Tiempo de respuesta: máximo 5.65ms, típico 3.84ms Figura A.10. Sensor fotoeléctrico. MARCAS COMERCIALES DE MICROCONTROLADORES  ATmega 16 (Atmel)  131 instrucciones (Arquitectura RISC)  32x8 registros de propósito general  16 KBytes de Memoria Flash dentro del sistema  512 Bytes de Memoria EEPROM  1Kbyte de SRAMFigura A.11. Empaques ATmega  2 Temporizadores/Contadores de 8 bits con pre-escaladores y comparadores separados, 1Temporizadores/Contadores de 16 bits con pre-escalador, modo de comparación y captura.  4 Canales PWM  8 Canales ADC de 10 bits  Comunicación serial USART  32 Puertos de I/O programables Figura A.12.Distribución de los pines.  Voltaje de operación: 4.5V – 5.5V para ATMega16, 2.5V – 5.5V para ATMega16L  Grado de velocidad: 0 – 16Mhz para ATMMega16, 0 – 8Mhz para ATMega16L Página | 11  PIC 16F877 (Microchip)  35 instrucciones (Arquitectura RISC)  8K x 14 palabras de Memoria FLASH.  368 x 8 Bytes de Memoria RAM  256x 8 Bytes de Memoria EEPROM Figura A.13.Empaques de PIC’s.  2 Temporizadores/Contadores de 8 bits con pre-escaladores y comparadores separados.  1 Temporizadores/Contadores de 16 bits con pre-escalador, modo de comparación y captura.  8 Canales ADC de 10 bits  Comunicación serial USART Figura A.14.Distribución de los pines de un PIC Página | 12 ANEXO 3 ANEXO 3.1.1 Cálculo del torque: Para hallar este parámetro se requerirá una carga máxima sobre la faja cuando ésta se encuentre en movimiento, es decir, se hallará el torque necesario para la carga máxima. Se aplicará el concepto de torque o momento de una fuerza respecto a un punto de referencia. Se hallará el torque necesario para mover la polea principal, para esto se hará uso de un bloque cuya masa es de 480gramos que se suspenderá a 17cm de la polea principal de la faja transportadora como se muestra en la figura 3.3. Figura 3.3. Descripción gráfica del cálculo del torque. Página | 13 Cálculo de la velocidad de giro del motor (RPM): Para el cálculo de la velocidad que deberá tener el motor, se tomará en cuenta la relación que existe entre la rapidez lineal y angular. La velocidad máxima a la que debería moverse la faja transportadora es de 0.7 m/s y el diámetro de la polea es 5 cm. Con estos datos podemos deducir lo siguiente: Cálculo de la potencia: El cálculo de la potencia de salida requerida del motor se puede realizar conociendo los dos parámetros ya mencionados [16]. Página | 14 ANEXO 3.1.2 Alternativas de solución para el actuador En la tabla 3.1 presenta un cuadro que muestra la comparación de las características más importantes de un motor DC sin escobillas y un motor DC con escobillas. Tabla 3.1. Comparación entre motores DC sin y con escobillas. Motor DC sin escobillas Motor DC con escobillas Característica Conmutación La conmutación es electrónica La conmutación es por escobillas. mediante sensores de efecto Hall. Mantenimiento Mínimo Periódico Durabilidad Mayor Menor Plana. Operación a todas las Moderada. Se reduce el par Curva Velocidad - Par velocidades con carga definida. debido al incremento de la fricción en las escobillas. Eficiencia Alta. No existe caída de tensión Moderada. debido a la ausencia de escobillas. Potencia - Tamaño Alta. Mejor disipación de calor ya Moderada. El calor es disipado que los devanados están en el en el interior aumentando la estator. temperatura. Alto. No existen limitaciones Baja. El límite se impone debido Rango de velocidad mecánicas por parte de las al uso de las escobillas. escobillas o el conmutador. Los arcos en las escobillas Ruido eléctrico Bajo. generan ruido causando EMI en equipos cercanos. Control Complejo y costoso. Simple y barato. Requisitos de control Necesidad de un controlador para Solo requiere un controlador si se operar el motor y variar la desea variar la velocidad. velocidad. Adaptado del libro “Electrónica de Potencia: circuitos, dispositivos y aplicaciones” de Muhammad H, Rashid [28]. Página | 15 También se analizará la posibilidad de usar un motor AC de inducción trifásico pues el sistema podría ser utilizado en un ambiente industrial. La comparación de las características más resaltantes frente a un motor DC sin escobillas, se detalla en la tabla 3.2. Tabla 3.2. Comparación entre motores DC sin escobillas y motores AC de inducción. Motor DC sin escobillas Motor AC de inducción Característica Curva velocidad y Plana. Permite operación a No lineal. A menor velocidad existe Torque cualquier velocidad con carga menor torque. nominal. Potencia de salida Alta. Es pequeño pues posee Moderada. Debido a los devanados imanes permanentes en el rotor. en el estator y rotor. Nominal. No es necesario un Hasta 7 veces la nominal. Se debe Corriente de circuito especial de arranque. contar con un circuito para el Arranque arranque. Requisitos de Es necesario un controlador Solo se requiere un controlador si control externo para ponerlo en marcha. se desea variar la velocidad. No sufre deslizamiento entre la Existe deslizamiento pues la Deslizamiento frecuencia del estator y rotor. frecuencia del rotor es menor que la del estator. Adaptado de la nota de aplicación “Brushless DC (BLDC) Motor Fundamentals”. Microchip Tecnology Inc. [28] Página | 16 ANEXO 3.2.1 Alternativas de solución para el interruptor de potencia Se tiene muchos tipos de transistores de potencia que cumplen de papel de interruptor de conmutación. Algunos de los más usados para este tipo de aplicaciones se muestran en la tabla 3.3, la cual ayudará a conocer un poco más de este tipo de interruptores y, de esta manera, elegir el más adecuado. Tabla 3.3. Comparación de interruptores de potencia. BJT MOSFET IGBT Característica Variable de control Corriente Voltaje Voltaje Frecuencia de Media Muy Alta Alta Conmutación (Hasta 25kHz) (Hasta casi 1MHz) (Hasta 100kHz) Especificaciones Hasta 1.5Kv Hasta 1kV Hasta 3.5kV máximas de voltaje Especificaciones Hasta 700 A Hasta 100 A Hasta 2kA máximas de corriente -Baja caída en estado -Baja pérdida de encendido. conmutación. -Poca potencia disipada Ventajas -Mayor capacidad de -Poca potencia en la compuerta. voltaje en estado disipada en -Bajo voltaje en estado apagado. compuerta. encendido. -Circuito simple de control de compuerta. -Disipación de potencia en activación -Menor capacidad de de base. voltaje en estado -Menor capacidad de Limitaciones -Requiere mayor apagado. voltaje en estado corriente de base para -Alta caída de voltaje apagado. sostener el estado en conducción. activo. -Altas disipaciones de conmutación. Adaptado de la nota de aplicación “Brushless DC (BLDC) Motor Fundamentals”. Microchip Tecnology Inc. [28] Página | 17 ANEXO 3.2.2 Aislamiento Eléctrico: Existe una etapa digital que se caracteriza principalmente por la generación de la onda PWM con frecuencia y ciclo de trabajo que se define en un primer momento. Luego se tendrá la posibilidad de variar el ciclo de trabajo a través de una interfaz de entrada externa como el teclado alfanumérico logrando así variar el voltaje promedio en los terminales del motor y, por ende, la velocidad de giro del mismo. La onda PWM será generada por un microcontrolador que se encontrará en una tarjeta impresa separada. A continuación, se usará un optoacoplador para aislar eléctricamente la etapa digital de la etapa de potencia mediante un diodo LED que satura o corta un fototransistor a través de emisión de luz. Para esto, cuando se quiera que el fototransistor se sature solo se debe hacer circular corriente por el diodo LED del optoacoplador y dejar de hacerlo cuando se quiere cortar al fototransistor. Como la señal PWM tiene una amplitud de 0V cuando está en baja y 4.2V como mínimo cuando está en alta, se puede aprovechar estos estados para controlar la emisión de luz del diodo LED del optoacoplador tal como se muestra en la figura 3.5. Figura 3.5. Circuito esquemático del bloque digital del variador de velocidad. Página | 18 Cálculos: El objetivo es generar una determinada cantidad de corriente para emitir luz al fototransistor del optoacoplador. Trabajaremos con los parámetros sugeridos en la hoja de datos del optoacoplador. De toda la gama de optoacopladores comerciales se eligió el 4N35 pues posee un mayor porcentaje de CTR (Current Transfer Ratio) lo que nos proporciona mayor corriente de colector cuando el fototransistor se satura. Según la hoja de datos del 4N35, el valor típico de la caída de voltaje en el diodo LED VF = 1.18V cuando circula a través de éste una corriente IF =1mA. En base a esto podemos hallar R1. Con este valor de R1, se modifica ligeramente el valor de la corriente. Página | 19 ANEXO 3.2.3 Etapa de Potencia: Se analizará los dos estados de la señal PWM, tanto en alta como en baja para ver el comportamiento de algunos de los componentes involucrados y poder calcular sus valores. Bloque de Acondicionamiento de la variable de control  Cuando la señal PWM está en 5V: En este estado el fototransistor se satura y su voltaje colector-emisor es igual a 0.3V. Luego debemos acondicionar la variable de control, es decir, el voltaje pues se usará un MOSFET como interruptor de potencia. El objetivo principal es que el voltaje que llegue al pin gate sea aproximadamente 12V. En el bloque de conmutación se explicará el motivo. Se debe aprovechar la saturación del fototransistor para que diseñar un circuito que genere 12V al pin gate del MOSFET. Para esto se usará una distribución de transistores y resistencias que cumplan el objetivo. En la figura 3.6 se propone el uso de un transistor PNP (Q1) que se saturará cuando el fototransistor también lo haga. La corriente máxima que se puede circular por el colector del fototransistor es aproximadamente 10mA pues el optoacoplador posee un 100% de CTR. El CTR es la relación de transferencia de corriente entre el diodo LED y el fototransistor. Para saturar el transistor Q1 debemos de cumplir algunos requisitos. Para esto, se debe recurrir a la hoja de datos del transistor 2N3906 para establecer los parámetros eléctricos de saturación.  Voltaje de Saturación Colector Emisor:  Ic = -10mA, Ib = -1mA @ típico -0.25V  Ic = -50mA, Ib = -5mA @ tipico-0.4V  Voltaje de Saturación Colector Emisor:  Ic = -10mA, Ib = -1mA @ mínimo -0.65V  Ic = -50mA, Ib = -5mA @ típico -0.95V Página | 20 Entonces, se fijará la corriente del colector del fototransistor en 1mA que a su vez será la corriente de base de transistor Q1. Tomando los valores máximos de saturación VEC = 0.25V y VEB = 0.85V @ IC = 10mA y IB = 1mA; y el voltaje de saturación VCE = 0.3V del fototransistor, se hallan las resistencias R2, R3 Y R4. Con este valor de R2 se puede hallar la corriente real que circula por el colector del fototransistor. La resistencia R3 es necesaria debido a que existe diferencia de potencial entre sus terminales cuando el transistor Q1 se satura. La corriente que se genere debido a esta diferencia de voltaje debe ser aproximadamente igual en comparación a la corriente que circula por el colector de fototransistor. Se asumirá que esta corriente aproximadamente 0.9mA ≅ 1mA. De esta manera, solo exigiremos una corriente de base del transistor Q1 IB de 0.1mA. Según este criterio se hallará la resistencia R3. La corriente real será: Para hallar R4 se tomará en cuenta la corriente del colector de Q1 en saturación ICQ1= 1mA ya que IB = 0.1mA; de esta manera cumplimos la condición ICQ1 = 10IB para garantizar la saturación. Entonces se tendrá la siguiente ecuación: La corriente real no variará tanto en comparación a la asumida: Página | 21 Luego de la etapa del transistor PNP, debemos de llevar la señal de 12V hacia la entrada del MOSFET, para esto se tiene un diodo de conmutación de alta velocidad que conducirá cuando el transistor Q1 se sature. En la hoja de datos del diodo 1N4148 se puede apreciar que el tiempo que demora en cambiar de modo de conducción a modo de corte. Alguna de éstas y otras características son las siguientes.  Trr= 4ns (Tiempo máximo de cambio de estado)  VF= 0.72V @ IF = 5mA (Ver gráfica para mayores detalles)  IFMÁX= 200mA  VR = 75V (Voltaje continuo máximo en inversa) Debido a la alta impedancia de entrada del MOSFET, se asume que la corriente que circula a través del diodo es mucho menor en comparación a la que circula por el colector del transistor Q1 ya además que es la necesaria para que el diodo conduzca. Finalmente la señal que llega al pin gate del MOSFET es un poco menos de 12V debido a las pequeñas caídas de tensiones; este valor sería aproximadamente:  Cuando la señal PWM está en 0V: En este caso, el fototransistor se encuentra en estado de corte, pues no circula corriente a través del LED interno del optoacoplador. De la misma manera, al no tener un camino hacia un menor potencial por el cual circule la corriente de base del transistor Q1, se produce el estado de corte del mismo. Bloque Interruptor de Potencia:  Cuando la señal PWM está en 5V: Esta etapa consta básicamente de la excitación de la puerta de un MOSFET a través de voltaje aplicado en ese terminal. El voltaje umbral para la conducción del MOSFET es VGS (TH)= 4.0V y admite un voltaje máximo de 20.0V por dicho terminal. Sin embargo, el voltaje que se aplica a la puerta es 11.03V aproximadamente debido a que la resistencia dinámica interna del MOSFET entre los terminales drenador y surtidor RDS disminuye a medida que se aumenta en voltaje aplicado en la puerta VG. Página | 22 Con un VG> VGS (TH), aseguramos que la caída de voltaje en los terminales drenador y surtidor sea el menor posible y que el motor reciba el voltaje completo. MOSFET Canal N Activo: VDD = 20V, Voltaje de control (VG) = 11.03V > VGS (TH) = 4.0V R (MOTOR) = 7Ω Si VGS= 10V (valor más cercano a 11.03V)  De las hojas de datos del MOSFET se obtiene: RDS (ON) = 15mΩ y la relación IDS = 50VDS en el supuesto caso que el MOSFET se encuentre en la región óhmica cuando se active. De la figura 3.7 se puede deducir dicha relación. Figura 3.7. Gráfica VDS vs IDS del MOSFET IRFZ44N. Se toma la parte lineal de la curva situada entre VDS [0 - 1.6V] e ID [0 - 80A] para plantear la siguiente ecuación: Reemplazando VDS = (0.02)*IDS en la siguiente ecuación del circuito proveniente de la figura 3.7. De la misma relación podemos encontrar el VDS: Página | 23 Luego aplicamos la condición: Se verifica entonces que el MOSFET se encuentra en la REGIÓN ÓHMICA.  Cuando la señal PWM está en 0V: El voltaje de control en la puerta del MOSFET VG= 0V. Entonces se tiene: Entonces el MOSFET se encuentra en la REGIÓN DE CORTE. Debemos de considerar los tiempos transitorios de conmutación en el MOSFET y asegurar que sean los más bajos posibles [32]. Se analizará el tiempo de conmutación de apagado del MOSFET en 2 momentos significativos: - Cuando el MOSFET tiende a cambiar de estado pero aún sigue activo. CGD: Capacitancia entre los terminales puerta y drenador VDS (ON)= 56.8mV De las gráficas proporcionadas en las hojas de datos se puede obtener los siguientes valores: Ciss = CDG + CGS, (El valor de CDG depende del voltaje VDS) Ciss = 2250pF - Cuando el MOSFET llega a la zona de corte y VDS = 20.0V Ciss = CDG + CGS Ciss = 1400pF Página | 24 El tiempo de total de transición en apagado es: τ1+ τ2 = 80.3ns Este tiempo de apagado que emplea el MOSFET se puede considerar despreciable en comparación al periodo de la señal de control del terminal gate de 10 ms. Para este caso, el MOSFET podrá cambiar de estado completamente tomando sus respectivos tiempos de establecimiento tanto para el apagado como para el encendido. Bloque de Motor DC:  Cuando la señal PWM está en 5V Debido a que el MOSFET se encuentra en estado de conducción, el motor DC recibe su voltaje nominal entre sus terminales y empieza a girar. Como la variación de su velocidad es por PWM, el motor recibe un voltaje promedio en relación al ciclo de trabajo de la señal PWM proporcionada por el microcontrolador.  Cuando la señal PWM está en 0V: El MOSFET se encuentra en estado de corte y no permite el flujo de corriente a través del motor. El motor tiende a parar su marcha. Además, existe otro efecto relacionado con la activación de cargas inductivas por conmutación de interruptores. Cuando se corta el flujo de corriente del motor en un tiempo muy corto, las bobinas tienden a generar voltajes muy elevados como respuesta a esa acción. Este efecto puede ocasionar daños al interruptor de potencia. Para liberar la energía atrapada en las bobinas, se coloca un diodo de efecto volante o “Free-Wheeling Diode” el cual entra en estado de conducción cuando el MOSFET se encuentre en estado de bloqueo y crea un camino por el cual descargar la corriente almacenada en las bobinas y llevarla hacia un condensador mostrado en el circuito esquemático. En la figura 3.8 se explica de gráficamente el efecto mencionado anteriormente. Figura 3.8.Acción del diodo volante para cargas inductivas [33]. Página | 25 Cálculo del disipador: Para poder calcular el disipador necesario para esta aplicación, es necesario calcular las pérdidas totales del MOSFET operando en conmutación[34]. En primer lugar se calculan las pérdidas en conducción, es decir, cuando el MOSFET esté cerrado y, por lo tanto haya circulación de corriente. Para este caso se considera que el MOSFET se comporta como una resistencia de valor R(ds)ON De la misma manera se toma en cuenta las pérdidas en conmutación que se producen cuando el semiconductor pasa del estado de bloqueo o corte a conducción y viceversa. De esta manera, la potencia total consumida en el MOSFET será: Finalmente procedemos al cálculo del disipador para el MOSFET con empaque TO- 220. Donde: Si se asume RƟJC = 1.5ºC/W y RƟCS = 0.5ºC/W Página | 26 Este resultado sugiere usar un disipador que posea una resistencia térmica no mayor a 611.14ºC/W. Debido a la poca potencia que disipa el MOSFET, se requiere un disipador con una resistividad térmica muy alta, lo que significa que cualquier disipador que posea una resistividad menor a la mencionada puede ser usado. Se tomará como referencia el disipador 6296B de la empresa AAVID THERMALLY con H = 50.8mm y resistencia térmica 3.6ºC/W mostrado en la figura 3.9 [35]. Figura 3.9. Disipador vertical para empaque TO-220. Página | 27 Anexo 3.3.1 Cálculo del tiempo de respuesta máximo para la detección de 5mm: Precisión 5mm T=   7.14ms @ 0.7m/s Velocidad 0.7m / s Tmáx = 7.14ms Cálculo frecuencia mínima de muestreo del sensor de presencia para realizar mediciones con precisión de 5mm: 280.12 Hz 1 1 f   140.06hz fs  2 f  fs  280.12Hz T max 7.14ms Tiempo de respuesta máximo del sensor de presencia para realizar mediciones con precisión de 5mm de una dimensión de una caja: 1 1 tr    3.57ms F max 280.12Hz Cálculo del tiempo de respuesta máximo para la detección de 1mm: 1mm T= 1.42ms @ 0.3m/s, entonces elegimos 0.7m / s Cálculo frecuencia mínima de muestreo del sensor de presencia para realizar mediciones con precisión de 1mm: 280.12 Hz 1 1 f    704.23hz fs  2 f  fs 1408.46Hz T max 1.42ms Tiempo de respuesta máximo del sensor de presencia para realizar mediciones con precisión de 1mm de una dimensión de una caja: 1 1 tr    0.71ms F max 1408.46Hz Página | 28 Cálculo frecuencia mínima de muestreo del ADC y sensores de distancia: Longitud .Minima.Caja tm  Velocidad 5cm 5cm  71.43ms 166.67ms 0.7m / s 0.3m / s 1 fs  2 fm fs  2x  fs  28hz 71.43ms Cálculo de sensibilidad del ADC y número de bits necesarios: Valor Teórico: - Voltaje de Referencia 5V. - 8 canales de ADC de 10 bits 5V Tenemos 20cm para un voltaje de 0 a 5V 1mm x  25mV 200mm 1LSB=25mV Número de bits necesarios para digitalizar la señal para alcanzar la precisión requerida (1mm): 5V 1LSB=23.8mV=  N  7.71 , entonces el mínimo número de bits 2N necesarios para digitalizar la señal del sensor de distancia será 8. Página | 29 Anexo 3.3.2 Tabla 3.4. Cuadro comparativo de alternativas de solución de Sensores de distancia Sensor Ultrasónico Modelo S18UUAR, Características Sensor Fotoeléctrico Modelo DT20 Hi 5 cables, 2m de longitud Fabricante Banner Engineering Sensor Intelligence Alimentación 10 a 30Vdc 10 – 30VDC 4-20mA Parámetros de salida 4-20mA modo PNP o NPN 2.5ms , cable negro conectado a 12Vcc (modo rápido de funcionamiento) Tiempo de respuesta Mayor a 2.5ms y menor a 15ms Rango de medición 30 a 300mm 3 a 60mm Modo manual y automática mediante Configuración y calibración Modo manual TEACH 2.5 ms response: ±1 mm 30 ms Linealidad [1] +/-2mm response: ± 0.5 mm Protección contra cortocircuito y polaridad Si No inversa en la salida Norma CE, diseño de equipos eléctricos dentro de ciertos límites de voltaje, Inmunidad al ruido compatibilidad electromagnética en las Norma CE[56] telecomunicaciones e inmunidad ante disturbios de esta clase. Frecuencia del ultrasonido 300khz @ 2.5ms - Precio $261 $680 Adaptado de “U-GAGE™ S18U Series Sensors with Analog Output” de Banner™ [37] y “DT20 HiDistance Sensor “de Sensor Intelligence [38]. Página | 30 Anexo 3.3.3 Tabla 3.5. Cuadro comparativo de alternativas de solución de Sensores de presencia. Sensor de Posición Fotodiodo Sensor Fotoeléctrico Modelo Características Q12AB6FF50 AD230-8-TO52 Fabricante Banner Engineering PacificSilicon Sensor Modo de operación Fixed-field, bipolar, operación por brillo Directo Voltaje de Alimentación 10 – 30Vdc Potencia disipada: 100mW@22°C Tiempo de Respuesta 700us Tiempo de subida: 0.18ns Rango de Medición 0.5 - 5mm 0.23mm de área activa 0.5mm @ 16mm de distancia, 6.5mm @50mm de distancia Tamaño del haz de luz 2mm - Apagado: 0V @ 10uA Corriente máxima de operación Señales de salida - Encendido: Vsat=1.45V @ 50mA Desde 0.3nA (Corriente oscura máxima 1.5nA) hasta 1mA Norma CE, diseño de equipos eléctricos dentro de ciertos límites de voltaje, Energía equivalente de ruido: Inmunidad al ruido compatibilidad electromagnética en las telecomunicaciones e inmunidad ante 1014W / Hz disturbios de esta clase. Circuito de Protección de Contra polarización inversa y voltajes No la fuente transitorios Circuito de Protección de Contra pulsos falsos y cortocircuitos No la Salidas 1: $63.84 5: $57.12 Precio $76 10: $52.08 50: $47.88 Adaptado de “WORLD-BEAM® Q12” de Banner™ [39] y “DT20 Hi Distance Sensor “de Sensor Intelligence [40]. Página | 31 Anexo 3.3.4 Diseño del circuito del acondicionamiento de señales del Sensor de Distancia (Sensor Ultrasónico) El sensor posee 5 terminales como se observa en la figura 3.10, los detalles de las conexiones se especifican a continuacion:  Cable marrón se conecta a la alimentacion del sensor, en este caso 12V  Cable azul se conecta al terminal negativo de la fuente de alimentacion.  Cable blanco es la salida del sensor, la carga se conecta entre este y el cable azul(terminal negativo)  Cable negro se utiliza para definir la velocidad de operación del sensor, rapida conectada de 5 a 30V o lenta 0 a 2V. En este caso se utilizará en modo rapido conectado a 12V.  Cable plomo utilizado para la configuracion automatica del sensor mediante modo TEACH.  Cable de metal que es un escudo para la atenuacion del ruido y proteccion contra cortocircuitos y cambios de polaridad del sensor. Según la hoja de datos de este dispositivo, las señales de salida del sensor son mejores V  3 cuando la carga total de resistencia es R  in  0.02  Corriente de salida del sensor: Is = 4 a 20mA 12  3  Resistencia de carga: R   450 0.02 Donde R= R3 + R4  Voltaje de salida del sensor: Vs = Is x 0.44KὨ  Vs= 1.76 – 8.8V  Elección de OPAMPS, en la tabla 3.6 se muestra las características más importantes de 2 OPAMPS que podrían utilizarse en la implementación del circuito de acondicionamiento. Página | 32 Tabla 3.6. Comparación de características más resaltantes de OPAMPS que se pueden emplear. Características UA741C LM324 Voltaje de Alimentación +/-15V +/-16V Rango de voltaje de entrada +/-15V -0.3 a 28.3V en modo común Desplazamiento de voltaje de 1 a 6mV típico 2mV, máximo 7mV entrada Ganancia en rechazo de modo 70-90DB común ( Rs 10K ): 70DB Mínimo +/-12V@, RL = 10KΩ típico +/-14V Limite alto a Vcc = 30V, RL  2K : 26V Voltaje de Salida Mínimo +/-12V@ RL<= 10KΩ Limite bajo a Vcc = 5V, RL  2K : Mínimo +/-10V@, R = 2kΩ, típico +/-13V típico 5mV, máximo 20mV L Máxima corriente de 0.2Ma 9Na desplazamiento en la entrada Tiempo de Respuesta 0.5V/μs 5V/μs (SlewRate) Adaptado de “LM124 LM224 - LM324 LOW POWER QUAD OPERATIONAL AMPLIFIERS” de On Semiconductor [41] y “ A741, A741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS” de Texas Instruments [42]. .  Utilización de OP-AMP’s LM324 como buffer para trasladar el voltaje al microcontrolador y no producir efecto de carga, elegido debido a las siguientes características:  Voltaje de entrada al buffer LM 324: Vin = 0.22kὨ x IsVin = 0.88V a 4.4V  Diodos de conmutación rápida 1N4148 para la protección contra cortocircuitos, sobretensiones o inversión de polaridad del microcontrolador, posee las siguientes características: [45] o Voltaje de Ruptura: 100V o Máxima Corriente umbral continuo: 450mA o Voltaje Umbral a If = 5mA: mínimo 0.62V, máximo 0.72V Página | 33  Voltaje de entrada al microcontrolador: Vμc = 0.88V a 4.4V  Potencia MAXIMA disipada por las resistencias: PR  Is 2 xR  PR  (20mA) 2 0.22K  88mW  Control remoto de los Sensores ultrasónicos: TEACH Características: [37] - TEACH remoto configurable a través del cable plomo. - Impedancia de entrada del TEACH: 12K - Ajuste de límites de medición máximo y mínimo de manera remota, y manual. Modo de funcionamiento y requerimientos: - El sensor requiere un estado lógico de 0V durante 0.05s para configurar los límites máximos y mínimos de medición. - Cuando el microcontrolador genera 5V, el cable plomo del sensor estará en alta impedancia. - Cuando el microcontrolador genera 0V, el conector plomo del sensor estará cortocircuitado con la tierra, voltaje en el cable plomo será 0V. Para la realización de los cálculos, se considerará en los transistores un sat 10 , Voltaje colector- emisor en saturaciónVce  0.2V , Voltaje base- emisor Vbe  0.7V a 25°C.  Voltaje de Microcontrolador igual a 5V, transistores T1 y T2 en corte (Igualmente T3 y T4 en el otro circuito), Vsensor es 6V.  Voltaje de Microcontrolador igual a 0V, transistores T1 y T2 saturados (Igualmente T3 y T4 en el otro circuito), En este estado hallamos el valor de todas las resistencias: o En la malla de Polarización de T1y T3 definimos la corriente de base IB1  0.1mA , entonces tenemos : Página | 34 V V R9  R12  uC be 5 0.7     43K I B 0.1mA Para fines prácticos elegimos la resistencia comercial de 47K Recalculando: VuC VI  be 5 0.7 B1 mA  mA  0.0915mA 47K 47K ICE1    IB1 100.0915mA 0.915mA Potencia disipada por la resistencia: PR  Is 2 xR  PR  (0.0915mA) 2 47K  0.393mW Se utilizarán resistencias de 0.25W o Malla de polarización de T2 y T4, definimos una IB 1mA VuC V V 5 0.2  0.7R10  R13  CE1 BE     41K I B2 0.1mA Se elegirá la resistencia comercial 39K Recalculando: VuC VCE1 VBE 5 0.2  0.7I B2  mA  mA  0.1051mA 39K 39K ICE2    IB2 100.1051mA1.051mA o En la malla de carga de T1: V V 5 0.2 R11 R14  uC CE1     530.685 ICE1  I B2 9.15 0.1051mA Se utilizará la resistencia comercial de 560 Página | 35 Anexo 3.3.5 Diseño del circuito del acondicionamiento de señales del Sensor de Presencia (Sensor Fotoeléctrico) Los cables de conexión del sensor se observan en la figura 3.12, cuyas funciones y caracteristicas se explican a continuación:  La alimentación del sensor conectada al cable marrón, para este caso 12V.  Terminal negativo de la alimentación conectado al cable azul.  El sensor tiene 2 tipos de salidas(Bipolar):  Fuente de Corriente o PNP, donde la carga está conetada al cable negro.(terminal positivo) y al cable azul (terminal negativo).  Disipador de corriente o NPN, donde la carga está conectada al cable marrón(terminal positivo a 12V) y al cable negro.(terminal negativo). Para el desarrollo de este trabajo se utilizará la configuracion PNP, cuando el sensor detecte la presencia de algún objeto se satura y produce una caída de potencial Vsat = 0.45V@ 50mA, de lo contrario actúa como circuito abierto y tiene un voltaje de salida igual 0V.  Voltaje de salida del Sensor cuando está saturado: Vs = Alimentación – Vsat Vs = 12 – 0.45 = 11.55V  Corriente máxima que entrega el sensor: 50mA @ 0.45V voltaje de saturación del sensor. Elegimos establecer una corriente de 2mA para un menor consumo de energía y no afecta en gran medida el voltaje de saturación del señor.  Cálculo de resistencias de carga, para ello se elige una corriente de operación del sensor de 2mA: VSalidaSensor 11.55 R7+R8=   5.75K , elegimos R7=R8= 3.3K Isensor 2mA Cálculo de la nueva corriente del sensor: VSalidaSensor 11.55 Isensor   1.75mA R7  R8 6.6K Página | 36  Potencia consumida por las P  Is2R xR  PR  (1.75mA) 2 3.3K  resistencias: 10.11mW Se elegirán resistencias de 0.25W  Utilización de OPAMPS LM324 como buffer para trasladar el voltaje a la salida y no producir efecto de carga [41].  Voltaje de entrada al buffer: Vin = 3.3kὨ x IsVin = 4.62V y Vin = 0.1V  Utilización de diodos de conmutación rápida 1N4148, para protección del microcontrolador ante cortocircuitos y voltajes altos o inversos [45].  Voltaje de entrada al microcontrolador: Vuc = 4.62V y 0.1V Página | 37 Anexo 3.4.1 Tabla 3.7. Cuadro comparativo de características más resaltantes de una pantalla LCD de caracteres y una gráfica. Pantalla LCD de caracteres MOP- Características AL204A-BYFY-25E-3IN Pantalla Grafica GDM12864 Transflectivo negativo con módulo Tipo backlight Transflectivo con módulo backlight Voltaje de alimentación (VDD) 4.5 – 5V 4.75 – 5.25V (76mmx25.2mm): Angulo de visión Mínimo: -20°C Mínimo: -40° (Fluido STN) Máximo: 35°C Máximo: 35° @Cr>2 Tamaño del caracter 2.95 x 4.75mm 0.39 x 0.39mm Radio de contraste 3 6 Escritura: 2.41ms Escritura: 2.61ms Tiempo (ciclo): Lectura: 2.98ms Lectura: 2.62ms Mínimo; 250ms Tiempo de respuesta Tsubida = Tbajada = 250ms Máximo: 300ms Corriente de operación (IDD) 1 – 10ma 1mA Mínimo: 0.7Vdd Voltaje de salida VDD Máximo: VDD Temperatura de operación -20 a 70 °C -20 a 70°C Total pines 16: Total pines 20:  8 pines de datos  8 pines de datos.  3 pines de control RS, R/W, CE  6 pines de control RES, CS1, CS2, Conexión de pines  2 pines de alimentación Vas y VDD R/W, D/I, E Página | 38 - 1 pin que regula el contraste Bo  3 pines de alimentación VDD y Vas y Ve(variable) - 2 pines de backlight: ánodo (+) y  1 pin que regula el contraste Bo cátodo (-)  2 pines de backlight: ánodo (+) y cátodo (-). Memoria CG-RAM 80B 107B y 108B Precio $24.01 $29.95 Adaptado de “MOP-AL204A Parallel Display Specifications” de Texas Matrix Orbital [46] y “User’s Guide GDM12864HLCM (Liquid Crystal Display Module)” de XIAMEN OCULAR OPTICS CO [47]. Página | 39 Anexo 3.4.2 Para regular el contraste de la pantalla se implementa el circuito mostrado en la figura 3.14, donde V0 se conecta a un potenciómetro de 10K y los otros 2 terminales de éste a 5V y a tierra respectivamente. Asimismo, para controlar el brillo o backlight, el pin BL- se conecta de forma similar a V0 a un potenciómetro de 5K con los otros 2 terminales de éste conectados a 5V y tierra, y además BL+ a fuente, como se observa en la figura 3.15. Fig. 3.14. Circuito de regulación del contraste Fig. 3.15. Circuito de regulación de brillo Página | 40 Anexo 3.5.1 Tabla 3.8. Comparación de características de uso de un teclado matricial y pulsadores Interruptor pulsador Modelo Kan- Características Teclado Matricial 38 Resistencia al agua y Si Agua y humedad polvo Tiempo de rebote  5ms - Voltaje máximo de 24Vdc 60Vdc operación Máxima corriente de 30Ma 100mA operación Resistencia de 100M@100V 100M@500V aislamiento Voltaje máximo soportado por el 250VRMS @60Hz por 1min 500v @60Hz 1 min dieléctrico Expectativa de vida 1000000 de operaciones 10000-50000 Interface de entrada 8 pines de acceso 16 pines de acceso Dimensiones 6.9 x 7.6cm - Precio S/.5.00 S/.0.10 Adaptado de 4x4 “Matrix Membrane Keypad” de Parallax[48] y “Interruptor de pulsador modelo no:Kan-38” de JialongElectron [49]. Página | 41 Anexo 3.5.2 En la implementación del teclado matricial, cada salida se conectará en configuración pull down con los puertos I/O del microcontrolador, como se ilustra en la figura 3.16. PC0 PC1 10K PC2 PC3 PC4 PC5 PC6 PC7 Figura 3.16. Modelo de conexión de un pulsador en el teclado matricial  Las entradas del microcontrolador son las filas del teclado y están conectados a los puertos PC4 a PC8.  Las salidas del microcontrolador son las columnas del teclado y corresponden a los puertos PC0 a PC1.  Si el pulsador está suelto, fluye corriente por la resistencia que es mínima 0.5mA, la entrada TTL del microcontrolador está en alto (5V) y la salida se encuentra en nivel bajo (0V).  Si el pulsador está presionado, fluye una corriente proveniente de la entrada TTL del microcontrolador (cortocircuito) hacia la salida, por lo tanto ésta se encuentra en nivel alto (5V). Página | 42 Anexo 3.6.1 Se enviarán 13 Bytes de datos a la computadora los cuales contendrán los valores del largo, alto, ancho en formato ASCII (3 bytes por cada dato) 3 caracteres @ para la separación de tales magnitudes y un byte de para la verificación de correcta transmisión. Lcajamaspequeña 0.05m ttx    71.43ms Velocidad .max ima. faja 0.7m / s 13Bytes 8 Vtx  1456bps 71.43ms La velocidad de transmisión de datos debe ser por lo menos 2 veces esta velocidad para asegurar la correcta transmisión de datos, valor que sería igual a 2912bps Página | 43 Anexo 3.6.2 Tabla 3.9. Cuadro comparativo de los tipos de comunicación de datos que pueden emplearse en el circuito de transmisión. Características RS485 RS232 Máxima longitud del cable Hasta 15m dependiendo de la velocidad Hasta 1200m para la transmisión de transmisión Tipo de comunicación Half y Full Duplex Half Duplex Velocidad de transmisión Hasta 2.5Mbps Hasta 9600bps Atenuación de ruido e Mucho mayor Regular interferencias Uso a nivel industrial Sí No Transmisión: 32 Transmisión: 2 Canales de comunicación Recepción: 32 Recepción: 2 Voltaje de entrada del transmisor MAX490 MAX490: -0.5V a Vcc+0.5V MAX232: -0.3V a Vcc+0.3V Voltaje de salida del receptor Voltaje de entrada del receptor MAX490: -8V a 12.5V MAX232: Vs(-)-0.3V a Vs(+)+0.3V Voltaje de salida del transmisor Precio S/. 24.00 S/.5.00 Adaptado de “Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers” [50] y “MAX220– MAX249 MAX220–MAX249 5V-Powered, Multichannel RS-232 Drivers/Receivers” de Maxim Integrated [51]. Página | 44 Anexo 3.6.3 Descripción de Pines de Conexión del circuito Integrado MAX490  TXD corresponde al pin de transmisión de datos del microcontrolador.  RXD corresponde al pin de recepción de datos del microcontrolador.  DI es el pin de entrada del controlador del MAX490, el número 3 en el CI del MAX490, un valor bajo de este establece una salida Y en nivel bajo y Z en alto, asimismo, un nivel alto fuerza un nivel alto en la salida Y y un nivel bajo en Z.  RO es el pin de recepción de salida, si la entrada de recepción A es mayor que B por 200mV, R0 estará en alto nivel, caso contrario se encontrará en nivel bajo. En el circuito mostrado corresponde al pin 2.  Y es la salida no invertida del controlador del MAX490, pin 5.  Z es la salida invertida del controlador del MAX490, pin 6.  A es la entrada no invertida para la recepción del MAX490, pin 8.  B es la entrada invertida del para la recepción del MAX490, pin 7.  Alimentación del circuito integrado Vcc por el pin 1, que variará en el rango de 4.75V y 5.35V  La tierra del circuito integrado es GND asignado al pin 4. Página | 45 Anexo 3.6.4 Tabla 3.10. Comparación de los tipos de protocolos que pueden emplearse en el circuito de recepción de datos. Características Conversor RS485 a RS232 y luego utilizar un Conversor RS485 a adaptador USB a RS232 USB mediante la utilización circuito integrado FT232 Interfaces estándares a Recepción mediante interfaz RS485 mediante Recepción mediante interfaz RS485 mediante utilizarse MAX490, conversión a interfaz RS232 mediante MAX490, conversión RS485 a USB mediante MAX232, y adaptador RS232 con conector DB9 FT232. a USB compatible con USB 1.1 y 2.0 Complejidad de diseño Menos complejo y bajo costo Más complejo y más costoso e implementación MAX232: 120Kbps MAX232: 120Kbps Velocidad máxima en MAX490: 2.5Mbps MAX490: 2.5Mbps baudios Adaptador USB-RS232: 921.6Kbaudios FT232: 300 baudios a 3Mbaudios para el estándar RS485 Windows7, Vista, XP, 2000ME, 98SE Windows 7, Vista, XP, 98, 98SE, ME, 2000, Server 2003 y 2008 Compatibilidad con Windows Server 2008 R2 Sistemas Operativos Windows XP embebidos Mac OS 10.x, Linux Mac OS 8/9, OS-X Adaptador USB-RS32: Circuito Integrado FT232: Buffer de Transmisión FIFO 192 Bytes en el buffer de recepción y 96 FIFO 256 Bytes en el buffer receptor y 128 y Recepción Bytes en el de transmisión Bytes en el de transmisión MAX232 : S/. 3.00 MAX490: S/. 23.00 Precio MAX490 : S/. 23.00 FT232: S/. 57.00 Adaptador USB-RS232: S/.18 Adaptado de “Conversor USB-RS232 (ZT-RS232B)” de Zone-Tek (HK) CompanyLimited [52] y “FT232R USB UART IC” de Future Technology Devices International Ltd. [53]. Página | 46 Anexo 3.6.5 Descripción de Pines de Conexión del circuito Integrado MAX232  T1IN pin de transmisión de datos de entrada del MAX232.  T1OUT pin de transmisión de datos de salida del MAX232.  R1IN pin de recepción de datos de entrada del MAX232.  R1OUT pin de recepción de datos para enviarlos como salida del MAX232.  Pin 2 de conector DB9 utilizado para la recepción de datos, pin 3 usado para la transmisión de datos y pin 5 para la conexión a tierra, la disposición de estos puntos de conexión se puede observar de mejor forma en la figura 3.19. Fig. 3.19. Diagrama de conexiones del conector DB9 Fig. 3.20. Tipos de Conectores USB Fig. 3.21. Diagrama de conexión del conector USB Tipo A Página | 47 Anexo 3.7.1 Tabla 3.12. Comparación de microcontroladores ATmega16 y7 PIC16F87. Comunicación Número Canales Canales de Memoria Memoria Set de Costo de datos de ADC temporización programa RAM instrucciones puertos de E/S ATmega16 1 USART 32 8 de 10 2 de 8 bits y 1 16KB 1KB 131 S/. 28 ATMEL bits de 16 bits 4 Empaque canales PWM superficial PIC16F877 1 USART 22 8 de 10 2 de 8bits y 1 8KB 1KB 35 S/. 20 MICROCHIP bits de 16bits Empaque superficial Adaptado de “8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega16-ATmega16L” de Atmel [54] y “PIC16F84A Data Sheet 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller” de Microchip [55]. Página | 48 Anexo 3.7. Fig. 3.22. Diagrama de conexiones del microcontrolador ATMega16 Página | 49 Descripción:  Teclado matricial de 4x4 conectado a todos los pines del puerto C configurado como entradas.  Pantalla LCD de 4x16 caracteres en modo de 4 bits conectado al puerto B configurado como salida de la siguiente forma:  Pin RS conectado a PD7  Pin R/W conectado a PB4  Pines de datos de DB4 a DB8 conectados a los puertos PB0 a PB3  Pin de activación de la pantalla E conectado a PB5 (Modo de 4 bits). - Comunicación USART a través del puerto de entrada PD0 como recepción y del puerto de salida PD1 para la transmisión de datos. - Canales de ADC conectados a los sensores ultrasónicos por los puertos de entrada PA0 y PA1 - Señales generadas por los sensores fotoeléctricos conectados a los pines de entrada PD2 y PD3 - Calibración en modo TEACH (automático) de los sensores ultrasónicos a partir de los puertos de entrada PA2 y PA3. - Control de velocidad a través del canal PWM del puerto PD5. - Conexión del programador del microcontrolador en los pines PB5 (MOSI), PB6 (MISO), PB7 (SCK) y RESET. - XTAL1 y XTAL2 para la inclusión de un cristal resonador externo de 1Mhz. - Utilización de los temporizadores 0, 1 y2 de la siguiente forma: o Temporizador 0, que corresponde al puerto PB3, utilizado para calcular el tiempo que demora una caja desde que activa el sensor fotoeléctrico 1 hasta su llegada al número 2. o Temporizador 2, que corresponde al puerto PD7, utilizado para registrar los valores de los datos del ADC cada 2ms. - Interrupciones externas INT0 y INT1 de los puertos PD2 y PD3, utilizados para detectar la activación de los sensores fotoeléctricos. Página | 50 Anexo 3.8.1 Tabla 3.13.Requerimientos eléctricos de la etapa de control. Dispositivo Voltaje (V) Corriente (mA) Potencia (mW) ATmega16A 5.0 15.0 75.0 Pantalla LCD 5.0 2.5 12.5 MAX490 5.0 0.5 2.5 Total 18.0 90.0 Tabla 3.14.Requerimientos eléctricos de la etapa de sensores. Dispositivo Voltaje (V) Corriente (mA) Potencia (W) Sensor Ultrasónico 12.0 65.0 (x2) 1.56 Sensor Fotoeléctrico 12.0 20.0 (x2) 0.48 LM324 12.0 3.0 (x4) 0.144 MMBT3906 VE= 5.0 IC= 10.0 (x2) 0.1 Total 98.0 2.2844 Tabla 3.15.Requerimientos eléctricos de la etapa de potencia. Dispositivo Voltaje (V) Corriente (mA) Potencia (W) Motor DC 20.0 3000 60.0 MMBT3906 VE= 12.0 IE= 1.0 (x2) 0.48 4N35 VC = 12.0 IC= 1.0 (x2) 0.1 Total 3002 60.58 Página | 51 Anexo 3.8.2 Tabla 3.17. Desempeño de una fuente de alimentación lineal versus una conmutada. Característica Fuentes lineales Fuentes conmutadas Eficiencia 45% - 55% 60% - 95% Regulación de línea 0.02% - 005% 0.05% - 0.1% Regulación de carga 0.02% - 0.1% 0.1% - 1.0% Voltaje de rizado en la salida 0.5mV - 2.0mVRMS 10mV - 100mVPP Proporción potencia – masa 22W/kg 88W/kg Ruido (EMI) Despreciable 50mV - 200mVPP Simplicidad en el diseño. Se agrega una etapa de control Complejidad Además de la etapa de por PWM. Presencia de rectificación, requiere solo un transformadores, inductores, circuito integrado y capacitores. transistores y filtros. Para potencias menores a 20W, El elaborado diseño y la Costo el precio de los componentes es inclusión de más elementos igual al de una fuente activos y pasivos encarecen el conmutada. En el mercado sistema. En páginas web: $ 50 local: S/.80 aprox. el precio barato. Adaptado de “Linear & Switching Voltage Regulator Handbook” de ON Semiconductor™ y “AN- 556 Introduction to Power Supplies” de Texas Instruments [57] y [58]. Página | 52 Anexo 3.8.3 Figura 3.23.Gráfica rfvs wCRL utilizada para hallar un rango de wCRL. Figura 3.24. Gráfica utilizada para hallar el parámetro RS/RL en %. Página | 53 Anexo 3.8.4 Diseño del filtro capacitivo de entrada: Primero se determina el valor de la resistencia de carga RLy se fija Vc (dc). Se adopta un valor de RS de: RS= 10%*(RL) =10%*(9.0) = 0.9Ω Establecemos un voltaje de rizado de 1.0Vppy hallamos un factor de rizado: Con este factor en la figura 3.23 hallamos un valor estimado para wCRL. Elegimos wCRL = 16. Luego hallamos CL: Considerando el nuevo valor de C, se halla el nuevo valor de wCRL. Luego, en la figura 3.24 se calcula la relación entre el voltaje dc a la salida del regulador y el valor máximo de voltaje en la salida del filtro. Este valor es el máximo valor de voltaje a la salida del transformador que se usaría. Para entenderlo en términos más simples, se pasará a magnitudes de voltajes eficaces. El valor RS es valor de la resistencia que posee el devanado secundario del transformador que se utiliza. El voltaje en el secundario del transformador debe ser aproximadamente 8.48VRMS. Página | 54 Fuente de alimentación de 12V: Diseño del filtro capacitivo de entrada: Primero se determina el valor de la resistencia de carga RL y se fija Vc (dc). Se adopta un valor de RS de: RS= 5%*(15) = 5%*(15) = 0.75Ω Establecemos un voltaje de rizado de 2.0Vppy hallamos un factor de rizado: Con este factor en la figura 3.23 hallamos un valor estimado para wCRL. Elegimos wCRL = 13. Luego hallamos C: Considerando el nuevo valor de C, se halla el nuevo valor de wCRL. Luego, en la figura 3.24 se calcula la relación entre voltaje dc a la salida del regulador y el valor máximo de voltaje en la salida del filtro. Este valor es el máximo valor de voltaje a la salida del transformador que se usaría. Para entenderlo en términos más simples, se pasará a magnitudes de voltajes eficaces. El valor RS es valor de la resistencia que posee el devanado secundario del transformador que se utiliza. El voltaje en el secundario del transformador debe ser aproximadamente 12.93 VRMS. Página | 55 Cabe resaltar que la salida de 5 voltios para la alimentación de los sensores, proviene de la fuente de alimentación de 5 voltios diseñada seguida de una etapa de filtrado por medio de una bobina y un condensador con los valores mostrados. Dicho filtro es el recomendado para aislar la etapa analógica de la digital según la hoja de datos del ATmega16 [54]. Cálculo del disipador: Para poder calcular el disipador en un regulador de voltaje es necesario conocer la diferencia de voltaje en la entrada y la salida del mismo, así como la corriente que proveerá al sistema que se desea alimentar. En primer lugar se debe conocer la potencia total disipada en el regulador de voltaje, para esto se hace un análisis con la siguiente ecuación [61]. Donde IL es la corriente de carga e Ig es la corriente de fuga del regulador. Para el regulador LM7805: Para el regulador LM7812: El siguiente parámetro a calcular es la temperatura máxima permitida en el componente y viene dado por la diferencia de la temperatura máxima en la juntura del empaque en el regulador (Tj) y la temperatura del medio ambiente donde está expuesto el dispositivo (Ta). Se asigna el parámetro Tj= 100ºC como factor de seguridad pese a que el regulador posee un Tj (máx)= 125ºC. Luego se calcula el máximo valor de resistencia térmica permitida entre la juntura del empaque y el medio ambiente para el caso del regulador LM7805. Página | 56 Debido a que la resistividad térmica ƟJA calculada es mucho mayor que la máxima permitida según la hoja de datos del regulador (ƟJA = 65ºC/W), no es necesario el uso de un disipador. De manera similar se realiza el análisis para el regulador LM7812. Se calcula la máxima resistencia térmica (ƟJA). Ya que la resistencia térmica hallada es mayor que la máxima permitida según la hoja de datos no es necesario el uso de un disipador. Como precaución se hace uso del mismo modelo del disipador usado en el MOSFET en conmutación para ambos reguladores de voltaje. Página | 57 Anexo 3.8.5 Diseño del filtro capacitivo de entrada: Tomamos en cuenta la nomenclatura mencionada anteriormente para el mismo cálculo. Primero se determina el valor de la resistencia de carga RLy se fija Vc (dc). Se adopta un valor de RS de: RS= 10%*(RL) = 10%*(8) = 0.8Ω Establecemos un voltaje de rizado de 2.0Vppy hallamos un factor de rizado: Con este factor en la figura 3.23 hallamos un valor estimado para wCRL. Elegimos wCRL = 16. Luego hallamos C: Considerando el nuevo valor de C, se halla el nuevo valor de wCRL. Luego, en la figura 3.24 se calcula la relación entre voltaje dc a la salida del regulador y el valor máximo de voltaje en la salida el del filtro. Este valor es el máximo valor de voltaje a la salida del transformador que se usaría. Para entenderlo en términos más simples, se pasará a magnitudes de voltajes eficaces. Página | 58 El voltaje en el secundario del transformador debe ser aproximadamente 20.20 VRMS. De la misma manera, se acoplará una etapa de regulación mediante el circuito integrado LM317, el cual proporcionará un voltaje ajustado a 20V. El voltaje a la salida del regulador se obtiene de acuerdo a la siguiente expresión: Donde el valor de la resistencia R1 se fija en 240Ω como sugerencia de la hoja de datos. Sin embargo, se optará por el valor comercial de 220Ω. El valor VOUT es el deseado, es decir, 20 voltios. Con estos datos se puede hallar R2. Para que ésta última fuente de alimentación pueda suministrar 4 amperios se hace uso del transistor de potencia PNP MJ2955 mostrado en la figura 3.26, el cual soporta un flujo de corriente continua de hasta 15 amperios por su colector. Se usa este transistor como un “bypass”, es decir un camino alterno por el cual una gran magnitud de corriente pueda circular ya que el regulador LM317 puede suministrar solo hasta 1.5 amperios. Figura 3.26.Transistor PNP MJ2955 empaque TO-3 La corriente que exige el sistema circulará por el colector del transistor de potencia cuando por la resistencia de 33Ω circule una determinada magnitud de corriente. Página | 59 Cuando lo anterior suceda, el transistor estará en la región de saturación y proveerá la corriente necesaria. Se analizará el caso de máxima corriente que puede proveer el transformador, es decir 4.0 amperios en el circuito esquemático mostrado en la figura 3.27. El voltaje de saturación del transistor MJ2955 es VBE = 1.8V. Para saturar al transistor se elige hfe(mín.) o β = 20. Cuando el transistor se satura se tiene la siguiente expresión: De esta manera la resistencia R1 actuará como sensor de corriente y cuando circule por el aproximadamente 250mA, el voltaje entre base y emisor del transistor de potencia será el suficiente para saturarlo. La resistencia R1 disipa una potencia de máxima P1 = (I 2 IN) x R1 = 2.0625 W y la resistencia R2 una potencia de P = (I ) 2 2 C x R2 = 3.52 W. Se usará resistencias de los valores mencionados para R1 y R2 con una capacidad de 5 vatios. Cálculo del disipador: Caso: Regulador LM317 El cálculo del disipador en el regulador ajustable LM317 es similar al análisis de lo realizado anteriormente para el regulador LM7805 o LM7812. Donde IL es la corriente de carga e Iadj es la corriente en el terminal de ajuste. Se asigna el parámetro Tj= 100ºC como factor de seguridad pese a que el regulador posee un Tj (máx)= 125ºC. Luego se calcula el máximo valor de resistencia térmica permitida entre la juntura del empaque y el medio ambiente. Página | 60 Debido a que la resistividad térmica ƟJA calculada es mayor que la máxima permitida según la hoja de datos del regulador (ƟJA = 50ºC/W), no es necesario el uso de un disipador; sin embargo, como precaución se hace uso del mismo modelo de disipador usado en el MOSFET en conmutación ya que ambos la resistencia térmica teórica es cercana a la máxima resistencia térmica permitida. Caso: Transistor MJ2955 Para el cálculo del disipador en el transistor de potencia se calcula la potencia disipada cuando éste se encuentra saturado y fluye corriente por su colector. Luego, procedemos a calcular la resistencia térmica entre la juntura del semiconductor y el medio ambiente [62]. La resistencia térmica RƟJA se puede representar como una suma de otras resistencias térmicas en el dispositivo semiconductor según la siguiente expresión: Si se asigna RƟJC = 1.52ºC/W (según hoja de datos) y RƟCS = 0.5ºC/W podemos obtener la resistencia térmica entre el disipador y el medio ambiente. Este resultado sugiere usar un disipador que posea una resistencia térmica no mayor a 26.38ºC/W. Se tomará como referencia el disipador modelo 575603 de la empresa AAVID THERMALLY con una resistencia térmica 7.2ºC/W mostrado en la figura 3.28 [56]. Página | 61 Figura 3.28. Disipador horizontal para empaque TO-3. Caso: Regulador LM7812 Para el caso del regulador LM7812 se recurre al análisis realizado anteriormente: Se asigna el parámetro Tj= 100ºC como factor de seguridad pese a que el regulador posee un Tj (máx)= 125ºC. Luego se calcula el máximo valor de resistencia térmica permitida entre la juntura del empaque y el medio ambiente. Debido a que la resistividad térmica ƟJA calculada es mucho mayor que la máxima permitida según la hoja de datos del regulador (ƟJA = 65ºC/W), no es necesario el uso de un disipador; sin embargo, como precaución se hace uso del mismo modelo de disipador usado en el MOSFET en conmutación. Página | 62 Anexo 3.9.1 MENU Inicialización de la pantalla LCD “MEDIDOR DE VOLUMEN” NO Menu? Muestra MENU “Primero debe NO calibrar sensores” 1? SI Se calibro? SI “Proceso iniciado” NO Muestra menu para subir y bajar la velocidad de la 2? SI faja transportadora NO NO Menu Calibrar NO 3? si Inicio proceso? “Primero debe si parar el proceso” NO Muestra las dimensiones de 4? si cada caja medida en tiempo real NO Activa o desactiva el envio 5? SI de datos a la PC NO Detiene todo el 6? proceso Figura 3.31. Diagrama de flujo de la tarea menú. Página | 63 Anexo 3.9.2 Tabla 3.21. Métodos de calibración de los sensores ultrasónicos. Procedimiento Resultado Botón Cable remoto 0.04<”clic”<0.8s 0.04s> 12,CR, ' Display 1st row 4-bit keypad value BIN4 keypad >> 8, CR, ' Display 2nd row 4-bit keypad value BIN4 keypad >> 4, CR, ' Display 3rd row 4-bit keypad value BIN4 keypad ' Display 4th row 4-bit keypad value Copyright © Parallax Inc. 4x4 Matrix Membrane Keypad (#27899) v1.2 12/16/2011 Page 3 of 5 IF keypad <> keypadOld THEN ' If different button is pressed, GOSUB Update ' update the keypad graphic to clear ENDIF ' old display IF keypad THEN ' Display button pressed in graphic GOSUB display ENDIF keypadOld = keypad ' Store keypad value in variable keypadOld LOOP ' -----[ Subroutine - ReadKeypad ]------------------------------------------------- ' Read keypad button states ReadKeypad: keypad = 0 OUTL = %00000000 ' Initialize IO DIRL = %00000000 FOR row = 0 TO 3 DIRB = %1111 ' Set columns (P7-P4) as outputs OUTB = %0000 ' Pull columns low (act as pull down) OUTA = 1 << row ' Set rows high one by one DIRA = 1 << row temp = 0 ' Reset temp variable to 0 FOR column = 0 TO 3 INPUT (column + 4) ' Set columns as inputs temp = temp | (INB & (1 << column)) ' Poll column state and store in temp NEXT keypad = keypad << 4 | (Temp REV 4) ' Store keypad value NEXT RETURN ' -----[ Subroutine - Update ]----------------------------------------------------- ' Graphical depiction of keypad Update: DEBUG CRSRXY,0,7, "+---+---+---+---+",CR, "| | | | |",CR, "+---+---+---+---+",CR, "| | | | |",CR, "+---+---+---+---+",CR, "| | | | |",CR, "+---+---+---+---+",CR, "| | | | |",CR, "+---+---+---+---+" RETURN ' -----[ Subroutine - Display ]---------------------------------------------------- ' Display button pressed in keypad graphic Display: IF KeyPad.BIT15 THEN DEBUG CRSRXY, 02,08,"1" IF Keypad.BIT14 THEN DEBUG CRSRXY, 06,08,"2" IF KeyPad.BIT13 THEN DEBUG CRSRXY, 10,08,"3" IF Keypad.BIT12 THEN DEBUG CRSRXY, 14,08,"A" IF KeyPad.BIT11 THEN DEBUG CRSRXY, 02,10,"4" IF Keypad.BIT10 THEN DEBUG CRSRXY, 06,10,"5" IF KeyPad.BIT9 THEN DEBUG CRSRXY, 10,10,"6" IF Keypad.BIT8 THEN DEBUG CRSRXY, 14,10,"B" IF KeyPad.BIT7 THEN DEBUG CRSRXY, 02,12,"7" IF Keypad.BIT6 THEN DEBUG CRSRXY, 06,12,"8" IF KeyPad.BIT5 THEN DEBUG CRSRXY, 10,12,"9" Copyright © Parallax Inc. 4x4 Matrix Membrane Keypad (#27899) v1.2 12/16/2011 Page 4 of 5 IF Keypad.BIT4 THEN DEBUG CRSRXY, 14,12,"C" IF KeyPad.BIT3 THEN DEBUG CRSRXY, 02,14,"*" IF Keypad.BIT2 THEN DEBUG CRSRXY, 06,14,"0" IF KeyPad.BIT1 THEN DEBUG CRSRXY, 10,14,"#" IF Keypad.BIT0 THEN DEBUG CRSRXY, 14,14,"D" RETURN Propeller™ P8X32A Example Code The example code below displays the button states of the 4x4 Matrix Membrane Keypad, and is a modified version of the 4x4 Keypad Reader DEMO object by Beau Schwabe. Note: This application uses the 4x4 Keypad Reader.spin object. It also uses the Parallax Serial Terminal to display the device output. Both objects and the Parallax Serial Terminal itself are included with the with the Propeller Tool v1.2.7 or higher, which is available from the Downloads link at www.parallax.com/Propeller. {{ 4x4 Keypad Reader PST.spin Returns the entire 4x4 keypad matrix into a single WORD variable indicating which buttons are pressed. }} CON _clkmode = xtal1 + pll16x _xinfreq = 5_000_000 OBJ text : "Parallax Serial Terminal" KP : "4x4 Keypad Reader" VAR word keypad PUB start 'start term text.start(115200) text.str(string(13,"4x4 Keypad Demo...")) text.position(1, 7) text.str(string(13,"RAW keypad value 'word'")) text.position(1, 13) text.str(string(13,"Note: Try pressing multiple keys")) repeat keypad := KP.ReadKeyPad '<-- One line command to read the 4x4 keypad text.position(5, 2) text.bin(keypad>>0, 4) 'Display 1st ROW text.position(5,3) text.bin(keypad>>4, 4) 'Display 2nd ROW text.position(5, 4) text.bin(keypad>>8, 4) 'Display 3rd ROW text.position(5, 5) text.bin(keypad>>12, 4) 'Display 4th ROW text.position(5, 9) text.bin(keypad, 16) 'Display RAW keypad value Revision History v1.0: original document v1.1: Updated Figure 1 on page 2 v1.2: Updated Figure 1 on page 2 (again); updated BS2 comments Copyright © Parallax Inc. 4x4 Matrix Membrane Keypad (#27899) v1.2 12/16/2011 Page 5 of 5 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Future Technology Devices International Ltd. FT232R USB UART IC The FT232R is a USB to serial UART FIFO receive and transmit buffers for high data throughput. interface with the following advanced features: Synchronous and asynchronous bit bang interface options with RD# and WR# strobes. Single chip USB to asynchronous serial data Device supplied pre-programmed with unique transfer interface. USB serial number. Entire USB protocol handled on the chip. No Supports bus powered, self powered and high- USB specific firmware programming required. power bus powered USB configurations. Fully integrated 1024 bit EEPROM storing Integrated +3.3V level converter for USB I/O. device descriptors and CBUS I/O configuration. Integrated level converter on UART and CBUS Fully integrated USB termination resistors. for interfacing to between +1.8V and +5V Fully integrated clock generation with no logic. external crystal required plus optional clock True 5V/3.3V/2.8V/1.8V CMOS drive output output selection enabling a glue-less interface and TTL input. to external MCU or FPGA. Configurable I/O pin output drive strength. Data transfer rates from 300 baud to 3 Mbaud (RS422, RS485, RS232 ) at TTL levels. Integrated power-on-reset circuit. 128 byte receive buffer and 256 byte transmit Fully integrated AVCC supply filtering - no buffer utilising buffer smoothing technology to external filtering required. allow for high data throughput. UART signal inversion option. FTDI‟s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the +3.3V (using external oscillator) to +5.25V requirement for USB driver development in (internal oscillator) Single Supply Operation. most cases. Low operating and USB suspend current. Unique USB FTDIChip-ID™ feature. Low USB bandwidth consumption. Configurable CBUS I/O pins. UHCI/OHCI/EHCI host controller compatible. Transmit and receive LED drive signals. USB 2.0 Full Speed compatible. UART interface support for 7 or 8 data bits, 1 -40°C to 85°C extended operating temperature or 2 stop bits and odd / even / mark / space / range. no parity Available in compact Pb-free 28 Pin SSOP and QFN-32 packages (both RoHS compliant). Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640 Copyright © 2010 Future Technology Devices International Limited 1 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 1 Typical Applications USB to RS232/RS422/RS485 Converters USB Industrial Control Upgrading Legacy Peripherals to USB USB MP3 Player Interface Cellular and Cordless Phone USB data transfer USB FLASH Card Reader and Writers cables and interfaces Set Top Box PC - USB interface Interfacing MCU/PLD/FPGA based designs to USB Digital Camera Interface USB USB Hardware Modems USB Audio and Low Bandwidth Video data transfer USB Wireless Modems PDA to USB data transfer USB Bar Code Readers USB Smart Card Readers USB Software and Hardware Encryption Dongles USB Instrumentation 1.1 Driver Support Royalty free VIRTUAL COM PORT Royalty free D2XX Direct Drivers (VCP) DRIVERS for... (USB Drivers + DLL S/W Interface) Windows 98, 98SE, ME, 2000, Server 2003, XP Windows 98, 98SE, ME, 2000, Server 2003, XP and Server 2008 and Server 2008 Windows 7 32,64-bit Windows 7 32,64-bit Windows XP and XP 64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows XP Embedded Windows CE 4.2, 5.0 and 6.0 Windows CE 4.2, 5.0 and 6.0 Mac OS 8/9, OS-X Linux 2.4 and greater Linux 2.4 and greater The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com). Various 3rd party drivers are also available for other operating systems - see FTDI website (www.ftdichip.com) for details. For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm 1.2 Part Numbers Part Number Package FT232RQ-xxxx 32 Pin QFN FT232RL-xxxx 28 Pin SSOP Note: Packing codes for xxxx is: - Reel: Taped and Reel, (SSOP is 2,000pcs per reel, QFN is 6,000pcs per reel). - Tube: Tube packing, 47pcs per tube (SSOP only) - Tray: Tray packing, 490pcs per tray (QFN only) For example: FT232RQ-Reel is 6,000pcs taped and reel packing Copyright © 2010 Future Technology Devices International Limited 2 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 1.3 USB Compliant The FT232R is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 40680004 (Rev B) and 40770018 (Rev C). Copyright © 2010 Future Technology Devices International Limited 3 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 2 FT232R Block Diagram VCC SLEEP# Baud Rate 48MHz Generator 3.3 Volt 3V3OUT LDO FIFO RX Regulator Buffer DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 USB Transceiver UART Controller DBUS5USBDP with Serial Interface with DBUS6 Engine USB UARTIntegrated Programmable DBUS7 Series ( SIE ) Protocol Engine FIFO Controller Signal Inversion USBDM Resistors and 1.5K CBUS0 Pull- up CBUS1 CBUS2 CBUS3 Internal CBUS4 EEPROM USB DPLL 3V3OUT FIFO TX Buffer OSCO (optional) Internal x4 Clock Reset 12MHz 48MHz RESET# Multiplier Generator OCSI Oscillator To USB Transeiver Cell (optional) TEST GND Figure 2.1 FT232R Block Diagram For a description of each function please refer to Section 4. Copyright © 2010 Future Technology Devices International Limited 4 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Table of Contents 1 Typical Applications ........................................................................ 2 1.1 Driver Support .................................................................................... 2 1.2 Part Numbers...................................................................................... 2 Note: Packing codes for xxxx is: .................................................................. 2 1.3 USB Compliant .................................................................................... 3 2 FT232R Block Diagram .................................................................... 4 3 Device Pin Out and Signal Description ............................................ 7 3.1 28-LD SSOP Package .......................................................................... 7 3.2 SSOP Package Pin Out Description ...................................................... 7 3.3 QFN-32 Package ............................................................................... 10 3.4 QFN-32 Package Signal Description .................................................. 10 3.5 CBUS Signal Options ......................................................................... 13 4 Function Description ..................................................................... 14 4.1 Key Features ..................................................................................... 14 4.2 Functional Block Descriptions ........................................................... 15 5 Devices Characteristics and Ratings .............................................. 17 5.1 Absolute Maximum Ratings............................................................... 17 5.2 DC Characteristics............................................................................. 18 5.3 EEPROM Reliability Characteristics ................................................... 21 5.4 Internal Clock Characteristics ........................................................... 21 6 USB Power Configurations ............................................................ 23 6.1 USB Bus Powered Configuration ...................................................... 23 6.2 Self Powered Configuration .............................................................. 24 6.3 USB Bus Powered with Power Switching Configuration .................... 25 6.4 USB Bus Powered with Selectable External Logic Supply .................. 26 7 Application Examples .................................................................... 27 7.1 USB to RS232 Converter ................................................................... 27 7.2 USB to RS485 Coverter ..................................................................... 28 7.3 USB to RS422 Converter ................................................................... 29 7.4 USB to MCU UART Interface .............................................................. 30 7.5 LED Interface .................................................................................... 31 7.6 Using the External Oscillator ............................................................ 32 8 Internal EEPROM Configuration .................................................... 33 9 Package Parameters ..................................................................... 35 9.1 SSOP-28 Package Dimensions .......................................................... 35 Copyright © 2010 Future Technology Devices International Limited 5 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.2 QFN-32 Package Dimensions ............................................................ 36 9.3 QFN-32 Package Typical Pad Layout ................................................. 37 9.4 QFN-32 Package Typical Solder Paste Diagram ................................. 37 9.5 Solder Reflow Profile ........................................................................ 38 10 Contact Information ................................................................... 39 Appendix A – References ........................................................................... 40 Appendix B - List of Figures and Tables ..................................................... 41 Appendix C - Revision History .................................................................... 43 Copyright © 2010 Future Technology Devices International Limited 6 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3 Device Pin Out and Signal Description 3.1 28-LD SSOP Package 4 TXD 28 OSCO VCCIO 1 TXD 1 20 VCC 5 DTR# OSCI RXD 16 USBDM 3 RTS# TEST RTS# 15 USBDP VCCIO AGND 11CTS# RXD NC FT232RL 2DTR# 8 NC RI# CBUS0 9 19 DSR# RESET# GND CBUS1 24 NC 10DCD# 27 NC GND OSCI 6 28 RI# OSCO DSR# VCC 23 CBUS0 DCD# RESET# 22 CBUS1 CTS# GND 17 3V3OUT 13 A T CBUS2 CBUS4 3V3OUT G G G G E 14 N N N N S CBUS3 CBUS2 USBDM D D D D T 12 CBUS4 CBUS3 14 15 USBDP 25 7 18 21 26 Figure 3.1 SSOP Package Pin Out and Schematic Symbol 3.2 SSOP Package Pin Out Description Note: The convention used throughout this document for active low signals is the signal name followed by a # Pin No. Name Type Description USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up 15 USBDP I/O resistor to 3.3V. 16 USBDM I/O USB Data Signal Minus, incorporating internal series resistor. Table 3.1 USB Interface Group Pin No. Name Type Description +1.8V to +5.25V supply to the UART Interface and CBUS group pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect this pin to 3V3OUT pin to drive out at +3.3V levels, or connect to VCC to drive out at 5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive 4 VCCIO PWR outputs at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used. 7, 18, GND PWR Device ground supply pins 21 Copyright © 2010 Future Technology Devices International Limited 7 XXXXXXXXXXXX FTDI YYXX-A FT232RL Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description +3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The main use of this pin is to provide the internal 17 3V3OUT Output +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. 20 VCC PWR +3.3V to +5.25V supply to the device core. (see Note 1) 25 AGND PWR Device analogue ground supply for internal clock multiplier Table 3.2 Power and Ground Group Pin No. Name Type Description 8, 24 NC NC No internal connection Active low reset pin. This can be used by an external device to reset the 19 RESET# Input FT232R. If not required can be left unconnected, or pulled up to VCC. Puts the device into IC test mode. Must be tied to GND for normal 26 TEST Input operation, otherwise the device will appear to fail. Input 12MHz Oscillator Cell. Optional – Can be left unconnected for 27 OSCI Input normal operation. (see Note 2) Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected 28 OSCO Output for normal operation if internal Oscillator is used. (see Note 2) Table 3.3 Miscellaneous Signal Group Pin No. Name Type Description 1 TXD Output Transmit Asynchronous Data Output. 2 DTR# Output Data Terminal Ready Control Output / Handshake Signal. 3 RTS# Output Request to Send Control Output / Handshake Signal. 5 RXD Input Receiving Asynchronous Data Input. Ring Indicator Control Input. When remote wake up is enabled in the 6 RI# Input internal EEPROM taking RI# low (20ms active low pulse) can be used to resume the PC USB host controller from suspend. 9 DSR# Input Data Set Ready Control Input / Handshake Signal. 10 DCD# Input Data Carrier Detect Control Input. 11 CTS# Input Clear To Send Control Input / Handshake Signal. Configurable CBUS output only Pin. Function of this pin is configured in 12 CBUS4 I/O the device internal EEPROM. Factory default configuration is SLEEP#. See CBUS Signal Options, Table 3.9. Configurable CBUS I/O Pin. Function of this pin is configured in the 13 CBUS2 I/O device internal EEPROM. Factory default configuration is TXDEN. See CBUS Signal Options, Table 3.9. Copyright © 2010 Future Technology Devices International Limited 8 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is PWREN#. See 14 CBUS3 I/O CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up. Configurable CBUS I/O Pin. Function of this pin is configured in the 22 CBUS1 I/O device internal EEPROM. Factory default configuration is RXLED#. See CBUS Signal Options, Table 3.9. Configurable CBUS I/O Pin. Function of this pin is configured in the 23 CBUS0 I/O device internal EEPROM. Factory default configuration is TXLED#. See CBUS Signal Options, Table 3.9. Table 3.4 UART Interface and CUSB Group (see note 3) Notes: 1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator. 2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R, please refer Section 7.6 3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM. Copyright © 2010 Future Technology Devices International Limited 9 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3.3 QFN-32 Package 32 25 1 24 1 VCCIO 30TXD FTDI 19 VCC 2RXD YYXX-A 15 USBDM 32 RTS# XXXXXXX 14 USBDP 8 5 CTS# NC 8 FT232RQ 17 12 NC FT232RQ 31DTR# 13 NC 9 16 6 25 DSR# NC 29 NC 7DCD# 18 3 25 26 27 28 29 30 31 32 RESET# RI# 23 NC 22 CBUS0 AGND 24 1 VCCIO 27 OSCI NC 23 2 RXD 28 OSCO 21CBUS1 CBUS0 22 3 RI# 16 3V3OUT CBUS1 21 4 GND 10 A T CBUS2 GND 20 5 NC G G G G E 11 VCC 19 6 DSR# N N N N S CBUS3 RESET# DCD# D D D D T18 7 9CBUS4 GND 17 8 CTS# 24 4 17 20 26 16 15 14 13 12 11 10 9 Figure 3.2 QFN-32 Package Pin Out and schematic symbol 3.4 QFN-32 Package Signal Description Pin No. Name Type Description USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor 14 USBDP I/O to +3.3V. 15 USBDM I/O USB Data Signal Minus, incorporating internal series resistor. Table 3.5 USB Interface Group Pin No. Name Type Description +1.8V to +5.25V supply for the UART Interface and CBUS group pins (2, 3, 6,7,8,9,10 11, 21, 22, 30,31,32). In USB bus powered designs connect this pin to 3V3OUT to drive out at +3.3V levels, or connect to VCC to drive out at +5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order 1 VCCIO PWR to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used. 4, 17, 20 GND PWR Device ground supply pins. Copyright © 2010 Future Technology Devices International Limited 10 RTS# CBUS4 DTR# CBUS2 TXD CBUS3 NC NC OSCO NC OSCI USBDP TEST USBDM NC 3V3OUT Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description +3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The purpose of this output is to provide the 16 3V3OUT Output internal +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. 19 VCC PWR +3.3V to +5.25V supply to the device core. (See Note 1). 24 AGND PWR Device analogue ground supply for internal clock multiplier. Table 3.6 Power and Ground Group Pin No. Name Type Description 5, 12, 13, 23, NC NC No internal connection. Do not connect. 25, 29 Active low reset. Can be used by an external device to reset the FT232R. If not 18 RESET# Input required can be left unconnected, or pulled up to VCC. Puts the device into IC test mode. Must be tied to GND for normal operation, 26 TEST Input otherwise the device will appear to fail. Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normal 27 OSCI Input operation. (See Note 2). Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected for normal 28 OSCO Output operation if internal Oscillator is used. (See Note 2). Table 3.7 Miscellaneous Signal Group Pin Name Type Description No. 30 TXD Output Transmit Asynchronous Data Output. 31 DTR# Output Data Terminal Ready Control Output / Handshake Signal. 32 RTS# Output Request to Send Control Output / Handshake Signal. 2 RXD Input Receiving Asynchronous Data Input. Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM 3 RI# Input taking RI# low (20ms active low pulse) can be used to resume the PC USB host controller from suspend. 6 DSR# Input Data Set Ready Control Input / Handshake Signal. 7 DCD# Input Data Carrier Detect Control Input. 8 CTS# Input Clear To Send Control Input / Handshake Signal. Configurable CBUS output only Pin. Function of this pin is configured in the device 9 CBUS4 I/O internal EEPROM. Factory default configuration is SLEEP#. See CBUS Signal Options, Table 3.9. Configurable CBUS I/O Pin. Function of this pin is configured in the device internal 10 CBUS2 I/O EEPROM. Factory default configuration is TXDEN. See CBUS Signal Options, Table 3.9. Copyright © 2010 Future Technology Devices International Limited 11 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin Name Type Description No. Configurable CBUS I/O Pin. Function of this pin is configured in the device internal 11 CBUS3 I/O EEPROM. Factory default configuration is PWREN#. See CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up. Configurable CBUS I/O Pin. Function of this pin is configured in the device internal 21 CBUS1 I/O EEPROM. Factory default configuration is RXLED#. See CBUS Signal Options, Table 3.9. Configurable CBUS I/O Pin. Function of this pin is configured in the device internal 22 CBUS0 I/O EEPROM. Factory default configuration is TXLED#. See CBUS Signal Options, Table 3.9. Table 3.8 UART Interface and CBUS Group (see note 3) Notes: 1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator. 2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R, please refer to Section 7.6. 3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM. Copyright © 2010 Future Technology Devices International Limited 12 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3.5 CBUS Signal Options The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both package versions of the FT232R. These options can be configured in the internal EEPROM using the software utility FT_PPROG or MPROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The default configuration is described in Section 8. CBUS Signal Available On CBUS Pin Description Option TXDEN CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Enable transmit data for RS485 Output is low after the device has been configured by USB, then high during USB suspend mode. This output can PWREN# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# in this way.* Transmit data LED drive: Data from USB Host to TXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 FT232R. Pulses low when transmitting data via USB. See Section 7.5 for more details. Receive data LED drive: Data from FT232R to USB Host. RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Pulses low when receiving data via USB. See Section 7.5 for more details. LED drive – pulses low when transmitting or receiving data TX&RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 via USB. See Section 7.5 for more details. Goes low during USB suspend mode. Typically used to SLEEP# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 power down an external TTL to RS232 level converter IC in USB to RS232 converter designs. CLK48 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 48MHz ±0.7% Clock output. ** CLK24 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 24 MHz Clock output.** CLK12 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 12 MHz Clock output.** CLK6 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 6 MHz ±0.7% Clock output. ** CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and CBUS3 in the CBitBangI/O CBUS0, CBUS1, CBUS2, CBUS3 internal EEPROM. A separate application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes in more detail how to use CBUS bit bang mode. Synchronous and asynchronous bit bang mode WR# BitBangWRn CBUS0, CBUS1, CBUS2, CBUS3 strobe output. Synchronous and asynchronous bit bang mode RD# strobe BitBangRDn CBUS0, CBUS1, CBUS2, CBUS3 output. Table 3.9 CBUS Configuration Control * PWREN# must be used with a 10kΩ resistor pull up. **When in USB suspend mode the outputs clocks are also suspended. Copyright © 2010 Future Technology Devices International Limited 13 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 4 Function Description The FT232R is a USB to serial UART interface device which simplifies USB to serial designs and reduces external component count by fully integrating an external EEPROM, USB termination resistors and an integrated clock circuit which requires no external crystal, into the device. It has been designed to operate efficiently with a USB host controller by using as little as possible of the total USB bandwidth available. 4.1 Key Features Functional Integration. Fully integrated EEPROM, USB termination resistors, clock generation, AVCC filtering, POR and LDO regulator. Configurable CBUS I/O Pin Options. The fully integrated EEPROM allows configuration of the Control Bus (CBUS) functionality, signal inversion and drive strength selection. There are 5 configurable CBUS I/O pins. These configurable options are 1. TXDEN - transmit enable for RS485 designs. 2. PWREN# - Power control for high power, bus powered designs. 3. TXLED# - for pulsing an LED upon transmission of data. 4. RXLED# - for pulsing an LED upon receiving data. 5. TX&RXLED# - which will pulse an LED upon transmission OR reception of data. 6. SLEEP# - indicates that the device going into USB suspend mode. 7. CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz, 12MHz, and 6MHz clock output signal options. The CBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing up to 4 general purpose I/O pins which are available during normal operation. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature. The CBUS lines can be configured with any one of these output options by setting bits in the internal EEPROM. The device is supplied with the most commonly used pin definitions pre-programmed - see Section 8 for details. Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT232R supports FTDI‟s previous chip generation bit-bang mode. In bit-bang mode, the eight UART lines can be switched from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate pre-scaler). With the FT232R device this mode has been enhanced by outputting the internal RD# and WR# strobes signals which can be used to allow external logic to be clocked by accesses to the bit-bang I/O bus. This option will be described more fully in a separate application note available from FTDI website (www.ftdichip.com). Synchronous Bit Bang Mode. The FT232R supports synchronous bit bang mode. This mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. This makes it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature. FTDIChip-ID™. The FT232R also includes the new FTDIChip-ID™ security dongle feature. This FTDIChip-ID™ feature allows a unique number to be burnt into each device during manufacture. This number cannot be reprogrammed. This number is only readable over USB and forms a basis of a security dongle which can be used to protect any customer application software being copied. This allows the possibility of using the FT232R in a dongle for software licensing. Further to this, a renewable license scheme can be implemented based on the FTDIChip-ID™ number when encrypted with other information. This encrypted number can be stored in the user area of the FT232R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID™ to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note, AN232R-02, available from FTDI website (www.ftdichip.com) describes this feature. The FT232R is capable of operating at a voltage supply between +3.3V and +5V with a nominal operational mode current of 15mA and a nominal USB suspend mode current of 70µA. This allows greater margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level converter within the UART interface allows the FT232R to interface to UART logic running at +1.8V, 2.5V, +3.3V or +5V. Copyright © 2010 Future Technology Devices International Limited 14 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 4.2 Functional Block Descriptions The following paragraphs detail each function within the FT232R. Please refer to the block diagram shown in Figure 2.1 Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other USB configuration descriptors. The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with the internal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM is available to system designers to allow storing additional data. The internal EEPROM descriptors can be programmed in circuit, over USB without any additional voltage requirement. It can be programmed using the FTDI utility software called MPROG, which can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). +3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, it can be used to supply external circuitry requiring a +3.3V nominal supply with a maximum current of 50mA. USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. This function also incorporates the internal USB series termination resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP. USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data signals for the Serial Interface Engine (SIE) block. Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz clock reference is used by the USB DPLL and the Baud Rate Generator blocks. Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data stream. USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the UART in accordance with the USB 2.0 specification chapter 9. FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the UART via the USB data OUT endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit register under control of the UART FIFO controller. (Rx relative to the USB interface). FIFO TX Buffer (256 bytes). Data from the UART receive register is stored in the TX buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data IN endpoint. (Tx relative to the USB interface). UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and TX buffers and the UART transmit and receive registers. UART Controller with Programmable Signal Inversion and High Drive. Together with the UART FIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serial and serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface. Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. The UART Controller also provides a transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and XON / XOFF handshaking options are also supported. Handshaking is handled in hardware to ensure fast response times. The UART interface also supports the RS232 BREAK setting and detection conditions. Copyright © 2010 Future Technology Devices International Limited 15 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Additionally, the UART signals can each be individually inverted and have a configurable high drive strength capability. Both these features are configurable in the EEPROM. Baud Rate Generator - The Baud Rate Generator provides a 16x clock input to the UART Controller from the 48MHz reference clock. It consists of a 14 bit pre-scaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction or “sub-integer”). This determines the baud rate of the UART, which is programmable from 183 baud to 3 Mbaud. The FT232R supports all standard baud rates and non-standard baud rates from 183 Baud up to 3 Mbaud. Achievable non-standard baud rates are calculated as follows - Baud Rate = 3000000 / (n + x) where „n‟ can be any integer between 2 and 16,384 ( = 214 ) and „x’ can be a sub-integer of the value 0, 0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values between 1 and 2 are not possible. This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud rate is required simply pass the required baud rate value to the driver as normal, and the FTDI driver will calculate the required divisor, and set the baud rate. See FTDI application note AN232B-05 on the FTDI website (www.ftdichip.com) for more details. RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input pin allows an external device to reset the FT232R. RESET# can be tied to VCC or left unconnected if not being used. Copyright © 2010 Future Technology Devices International Limited 16 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 5 Devices Characteristics and Ratings 5.1 Absolute Maximum Ratings The absolute maximum ratings for the FT232R devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter Value Unit Storage Temperature -65°C to 150°C Degrees C 168 Hours Floor Life (Out of Bag) At Factory Ambient (IPC/JEDEC J-STD-033A MSL Level 3 Hours (30°C / 60% Relative Humidity) Compliant)* Ambient Temperature (Power Applied) -40°C to 85°C Degrees C MTTF FT232RL 11162037 hours MTTF FT232RQ 4464815 hours VCC Supply Voltage -0.5 to +6.00 V DC Input Voltage – USBDP and USBDM -0.5 to +3.8 V DC Input Voltage – High Impedance -0.5 to + (VCC +0.5) V Bidirectionals DC Input Voltage – All Other Inputs -0.5 to + (VCC +0.5) V DC Output Current – Outputs 24 mA DC Output Current – Low Impedance 24 mA Bidirectionals Power Dissipation (VCC = 5.25V) 500 mW Table 5.1 Absolute Maximum Ratings * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours. Copyright © 2010 Future Technology Devices International Limited 17 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 5.2 DC Characteristics DC Characteristics (Ambient Temperature = -40°C to +85°C) Parameter Description Minimum Typical Maximum Units Conditions VCC Operating Supply Using Internal VCC1 4.0 --- 5.25 V Voltage Oscillator VCC Operating Supply Using External VCC1 3.3 --- 5.25 V Voltage Crystal VCCIO Operating VCC2 1.8 --- 5.25 V Supply Voltage Operating Supply Icc1 --- 15 --- mA Normal Operation Current Operating Supply Icc2 50 70 100 μA USB Suspend Current 3V3 3.3v regulator output 3.0 3.3 3.6 V Table 5.2 Operating Voltage and Current Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3.2 4.1 4.9 V I source = 2mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 2mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.2 2.7 3.2 V I source = 1mA Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) Copyright © 2010 Future Technology Devices International Limited 18 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.6 2.8 V I source = 1mA Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 1.32 1.62 1.8 V I source = 0.2mA Vol Output Voltage Low 0.06 0.1 0.18 V I sink = 0.5mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3.2 4.1 4.9 V I source = 6mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 6mA Vin Input Switching 1.0 1.2 1.5 V ** Threshold VHys Input Switching 20 25 30 mV ** Hysteresis Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.2 2.8 3.2 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) Copyright © 2010 Future Technology Devices International Limited 19 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.6 2.8 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 1.35 1.67 1.8 V I source = 0.4mA Vol Output Voltage Low 0.12 0.18 0.35 V I sink = 3mA Input Switching Vin 1.0 1.2 1.5 V ** Threshold Input Switching VHys 20 25 30 mV ** Hysteresis Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ** Only input pins have an internal 200KΩ pull-up resistor to VCCIO Parameter Description Minimum Typical Maximum Units Conditions Input Switching Vin 1.3 1.6 1.9 V Threshold Input Switching VHys 50 55 60 mV Hysteresis Table 5.11 RESET# and TEST Pin Characteristics Copyright © 2010 Future Technology Devices International Limited 20 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions RI = 1.5kΩ to I/O Pins Static Output UVoh 2.8 3.6 V 3V3OUT (D+) RI = (High) 15KΩ to GND (D-) RI = 1.5kΩ to I/O Pins Static Output UVol 0 0.3 V 3V3OUT (D+) RI = (Low) 15kΩ to GND (D-) Single Ended Rx UVse 0.8 2.0 V Threshold Differential Common UCom 0.8 2.5 V Mode Differential Input UVDif 0.2 V Sensitivity Driver Output UDrvZ 26 29 44 Ohms See Note 1 Impedance Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics 5.3 EEPROM Reliability Characteristics The internal 1024 Bit EEPROM has the following reliability characteristics: Parameter Value Unit Data Retention 10 Years Read / Write Cycle 10,000 Cycles Table 5.13 EEPROM Characteristics 5.4 Internal Clock Characteristics The internal Clock Oscillator has the following characteristics: Value Parameter Unit Minimum Typical Maximum Frequency of Operation 11.98 12.00 12.02 MHz (see Note 1) Clock Period 83.19 83.33 83.47 ns Duty Cycle 45 50 55 % Table 5.14 Internal Clock Characteristics Note 1: Equivalent to +/-1667ppm Copyright © 2010 Future Technology Devices International Limited 21 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions I source = Voh Output Voltage High 2.1 2.8 3.2 V 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 Note1: When supplied, the FT232R is configured to use its internal clock oscillator. These characteristics only apply when an external oscillator or crystal is used. Copyright © 2010 Future Technology Devices International Limited 22 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6 USB Power Configurations The following sections illustrate possible USB power configurations for the FT232R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package options. All USB power configurations illustrated apply to both package options for the FT232R device. Please refer to Section 3 for the package option pin-out and signal descriptions. 6.1 USB Bus Powered Configuration Ferrite Vcc TXD 1 Bead VCC RXD 2 USBDM RTS# 3 USBDP CTS# 4 10nF VCCIO FT232R+ DTR# 5 NC DSR# RESET# SHIELD NC DCD# OSCI RI# GND OSCO CBUS0 Vcc CBUS1 3V3OUT 100nF 4.7uF + A T CBUS2 G G G G E N N N N S CBUS3 100nF D D D D T CBUS4 GND GND GND Figure 6.1 Bus Powered Configuration Figure 6.1 Illustrates the FT232R in a typical USB bus powered design configuration. A USB bus powered device gets its power from the USB bus. Basic rules for USB bus power devices are as follows – i) On plug-in to USB, the device should draw no more current than 100mA. ii) In USB Suspend mode the device should draw no more than 2.5mA. iii) A bus powered high power USB device (one that draws more than 100mA) should use one of the CBUS pins configured as PWREN# and use it to keep the current below 100mA on plug-in and 2.5mA on USB suspend. iv) A device that consumes more than 100mA cannot be plugged into a USB bus powered hub. v) No device can draw more than 500mA from the USB bus. The power descriptors in the internal EEPROM of the FT232R should be programmed to match the current drawn by the device. A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT232R and associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from Steward (www.steward.com), for example Steward Part # MI0805K400R-10. Note: If using PWREN# (available using the CBUS) the pin should be pulled to VCCIO using a 10kΩ resistor. Copyright © 2010 Future Technology Devices International Limited 23 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.2 Self Powered Configuration Figure 6.2 Self Powered Configuration Figure 6.2 illustrates the FT232R in a typical USB self powered configuration. A USB self powered device gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic rules for USB self powered devices are as follows – i) A self powered device should not force current down the USB bus when the USB host or hub controller is powered down. ii) A self powered device can use as much current as it needs during normal operation and USB suspend as it has its own power supply. iii) A self powered device can be used with any USB host, a bus powered USB hub or a self powered USB hub. The power descriptor in the internal EEPROM of the FT232R should be programmed to a value of zero (self powered). In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the RESET# pin of the FT232R device. When the USB host or hub is powered up an internal 1.5kΩ resistor on USBDP is pulled up to +3.3V (generated using the 4K7 and 10k resistor network), thus identifying the device as a full speed device to the USB host or hub. When the USB host or hub is powered off, RESET# will be low and the FT232R is held in reset. Since RESET# is low, the internal 1.5kΩ resistor is not pulled up to any power supply (hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to do this may cause some USB host or hub controllers to power up erratically. Figure 6.2 illustrates a self powered design which has a +4V to +5.25V supply. Note: 1. When the FT232R is in reset, the UART interface I/O pins are tri-stated. Input pins have internal 200kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. 2. When using internal FT232R oscillator the VCC supply voltage range must be +4.0V to 5.25V. 3. When using external oscillator the VCC supply voltage range must be +3.3V to 5.25V Any design which interfaces to +3.3 V or +1.8V would be having a +3.3V or +1.8V supply to VCCIO. Copyright © 2010 Future Technology Devices International Limited 24 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.3 USB Bus Powered with Power Switching Configuration P-Channel Power MOSFET s d Switched 5V Power To External Logic g 0.1uF 0.1uF Soft Start Circuit 1K Ferrite Bead 1 5V VCC TXD VCC 2 RXD USBDM 3 RTS# USBDP CTS# 4 10nF + VCCIO DTR# FT232R 5 NC DSR# RESET# DCD# SHIELD NC RI# 5V VCC OSCI GND CBUS0 OSCO 5V VCC CBUS1 10K 3V3OUT CBUS2 100nF 4.7uF T PWREN#+ A CBUS3 G G G G E N N N N S CBUS4 100nF D D D D T GND GND GND Figure 6.3 Bus Powered with Power Switching Configuration A requirement of USB bus powered applications, is when in USB suspend mode, the application draws a total current of less than 2.5mA. This requirement includes external logic. Some external logic has the ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic that cannot power itself down in this way, the FT232R provides a simple but effective method of turning off power during the USB suspend mode. Figure 6.3 shows an example of using a discrete P-Channel MOSFET to control the power to external logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the transient power surge, caused when the MOSFET switches on, will reset the FT232R or the USB host/hub controller. The soft start circuit example shown in Figure 6.3 powers up with a slew rate of approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V in approximately 400 microseconds. As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or equivalent. With power switching controlled designs the following should be noted: i) The external logic to which the power is being switched should have its own reset circuitry to automatically reset the logic when power is re-applied when moving out of suspend mode. ii) Set the Pull-down on Suspend option in the internal FT232R EEPROM. iii) One of the CBUS Pins should be configured as PWREN# in the internal FT232R EEPROM, and used to switch the power supply to the external circuitry. This should be pulled high through a 10 kΩ resistor. iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up to 500mA of current from the USB bus), the power consumption of the application must be set in the Max Power field in the internal FT232R EEPROM. A high-power bus powered application uses the descriptor in the internal FT232R EEPROM to inform the system of its power requirements. v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered down using the external logic. In this case use the +3V3OUT. Copyright © 2010 Future Technology Devices International Limited 25 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.4 USB Bus Powered with Selectable External Logic Supply 3.3V or 5V Supply to VCCIO External Logic Vcc 100nF Ferrite TXD 1 Bead VCC RXD 2 USBDM RTS# 3 USBDP CTS# 4 1 10nF 2 VCCIO FT232R+ DTR# 5 3 NC DSR# RESET# SHIELD Jumper NC DCD# OSCI GND RI# OSCO Vcc CBUS0 VCCIO 100nF 4.7uF CBUS1+ 10K 3V3OUT CBUS2 100nF A T G G G G E PWREN# N N N N S CBUS3 D D D D T SLEEP# CBUS4 GND GND GND Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply Figure 6.4 illustrates a USB bus power application with selectable external logic supply. The external logic can be selected between +3.3V and +5V using the jumper switch. This jumper is used to allow the FT232R to be interfaced with a +3.3V or +5V logic devices. The VCCIO pin is either supplied with +5V from the USB bus (jumper pins1 and 2 connected), or from the +3.3V output from the FT232R 3V3OUT pin (jumper pins 2 and 3 connected). The supply to VCCIO is also used to supply external logic. With bus powered applications, the following should be noted: i) To comply with the 2.5mA current supply limit during USB suspend mode, PWREN# or SLEEP# signals should be used to power down external logic in this mode. If this is not possible, use the configuration shown in Section 6.3. ii) The maximum current sourced from the USB bus during normal operation should not exceed 100mA, otherwise a bus powered design with power switching (Section 6.3) should be used. Another possible configuration could use a discrete low dropout (LDO) regulator which is supplied by the 5V on the USB bus to supply between +1.8V and +2.8V to the VCCIO pin and to the external logic. In this case VCC would be supplied with the +5V from the USB bus and the VCCIO would be supplied from the output of the LDO regulator. This results in the FT232R I/O pins driving out at between +1.8V and +2.8V logic levels. For a USB bus powered application, it is important to consider the following when selecting the regulator: i) The regulator must be capable of sustaining its output voltage with an input voltage of +4.35V. An Low Drop Out (LDO) regulator should be selected. ii) The quiescent current of the regulator must be low enough to meet the total current requirement of <= 2.5mA during USB suspend mode. A suitable series of LDO regulators that meets these requirements is the MicroChip/Telcom (www.microchip.com) TC55 series of devices. These devices can supply up to 250mA current and have a quiescent current of under 1μA. Copyright © 2010 Future Technology Devices International Limited 26 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7 Application Examples The following sections illustrate possible applications of the FT232R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package options. 7.1 USB to RS232 Converter VCC VCC VCC Ferrite Bead TXD 1 TXD TXDATA VCC RXD 2 RXD RXDATA GND USBDM 5 DB9M RTS# RTS# RTS 93 RI USBDP 270R 270RCTS# DTR 4 CTS# CTS 8 4 CTS 10nF 3+ VCCIO DTR# TXDATA DTR# DTR RTS 7 FT232R RXDATA 2 5 NC DSR# 6DSR# DSR DSR 1 DCD RESET# DCD# DCD# DCD SHIELD 10 SHIELD NC RI# RI# RI OSCI SHDN# GND CBUS0 TXLED# OSCO RXLED# VCC CBUS1 3V3OUT CBUS2 GPIO2 100nF 4.7uF + A T CBUS3 GPIO3 G G G G E N N N N S CBUS4 100nF D D D D T SLEEP# GND GND GND Figure 7.1 Application Example showing USB to RS232 Converter An example of using the FT232R as a USB to RS232 converter is illustrated in Figure 7.1. In this application, a TTL to RS232 Level Converter IC is used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS232 levels. This level shift can be done using the popular “213” series of TTL to RS232 level converters. These “213” devices typically have 4 transmitters and 5 receivers in a 28-LD SSOP package and feature an in-built voltage converter to convert the +5V (nominal) VCC to the +/- 9 volts required by RS232. A useful feature of these devices is the SHDN# pin which can be used to power down the device to a low quiescent current during USB suspend mode. A suitable level shifting device is the Sipex SP213EHCA which is capable of RS232 communication at up to 500k baud. If a lower baud rate is acceptable, then several pin compatible alternatives are available such as the Sipex SP213ECA, the Maxim MAX213CAI and the Analogue Devices ADM213E, which are all suitable for communication at up to 115.2k baud. If a higher baud rate is required, the Maxim MAX3245CAI device is capable of RS232 communication rates up to 1Mbaud. Note that the MAX3245 is not pin compatible with the 213 series devices and that the SHDN pin on the MAX device is active high and should be connect to PWREN# pin instead of SLEEP# pin. In example shown, the CBUS0 and CBUS1 have been configured as TXLED# and RXLED# and are being used to drive two LEDs. Copyright © 2010 Future Technology Devices International Limited 27 RS232 LEVEL CONVERTER Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.2 USB to RS485 Coverter Vcc Vcc RS485 LEVEL CONVERTER GND DB9M 3 7 Ferrite Bead TXD 1 TXD VCC 4 RXD 2 RXD 6 USBDM 2 3 RTS# USBDP CTS# 1 4 SHIELD 10 10nF + VCCIO DTR# FT232R SP481 NC 120R5 DSR# 5 RESET# DCD# Link SHIELD NC RI# OSCI VCCIO GND CBUS0 GPIO0 OSCO Vcc CBUS1 GPIO1 10K CBUS2 3V3OUT TXDEN 100nF 4.7uF + A T CBUS3 G G G G E PWREN# N N N N S CBUS4 GPO 100nF D D D D T GND GND GND Figure 7.2 Application Example Showing USB to RS485 Converter An example of using the FT232R as a USB to RS485 converter is shown in Figure 7.2. In this application, a TTL to RS485 level converter IC is used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS485 levels. This example uses the Sipex SP481 device. Equivalent devices are available from Maxim and Analogue Devices. The SP481 is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN signal CBUS pin option on the FT232R is provided for exactly this purpose and so the transmitter enable is wired to CBUS2 which has been configured as TXDEN. Similarly, CBUS3 has been configured as PWREN#. This signal is used to control the SP481‟s receiver enable. The receiver enable is active low, so it is wired to the PWREN# pin to disable the receiver when in USB suspend mode. CBUS2 = TXDEN and CBUS3 = PWREN# are the default device configurations of the FT232R pins. RS485 is a multi-drop network; so many devices can communicate with each other over a two wire cable interface. The RS485 cable requires to be terminated at each end of the cable. A link (which provides the 120Ω termination) allows the cable to be terminated if the SP481 is physically positioned at either end of the cable. In this example the data transmitted by the FT232R is also present on the receive path of the SP481.This is a common feature of RS485 and requires the application software to remove the transmitted data from the received data stream. With the FT232R it is possible to do this entirely in hardware by modifying the example shown in Figure 7.2 by logically OR‟ing the FT232R TXDEN and the SP481 receiver output and connecting the output of the OR gate to the RXD of the FT232R. Note that the TXDEN is activated 1 bit period before the start bit. TXDEN is deactivated at the same time as the stop bit. This is not configurable. Copyright © 2010 Future Technology Devices International Limited 28 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.3 USB to RS422 Converter Vcc Vcc RS422 LEVEL 4 CONVERTER 10 Ferrite Bead 5 TXDM 1 TXD VCC 9 TXDP 2 RXD 3 RXDP USBDM 3 RTS# 11 USBDP 2 12 120R CTS# 4 10nF + VCCIO DTR# FT232R SP491 RXDM GND 5 NC DSR# 6 7 DB9M RESET# TXDM DCD# TXDP Vcc NC RXDPSHIELD RI# RXDM OSCI RTSM GND CBUS0 RTSP OSCO RS422 LEVEL CTSP CONVERTER CTSM Vcc CBUS1 4 SHIELD 3V3OUT CBUS2 10 RTSM 100nF 4.7uF + 5A T CBUS3 9 G G G G E PWREN# RTSP N N N N S CBUS4- 3 CTSP 100nF D D D D T SLEEP# 11 2 12 120R GND GND Vcc SP491 CTSM 6 7 GND 10K Figure 7.3 USB to RS422 Converter Configuration An example of using the FT232R as a USB to RS422 converter is shown in Figure 7.3. In this application, two TTL to RS422 Level Converter ICs are used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS422 levels. There are many suitable level converter devices available. This example uses Sipex SP491 devices which have enables on both the transmitter and receiver. Since the SP491 transmitter enable is active high, it is connected to a CBUS pin in SLEEP# configuration. The SP491 receiver enable is active low and is therefore connected to a CBUS pin PWREN# configuration. This ensures that when both the SP491 transmitters and receivers are enabled then the device is active, and when the device is in USB suspend mode, the SP491 transmitters and receivers are disabled. If a similar application is used, but the design is USB BUS powered, it may be necessary to use a P-Channel logic level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to ensure that the USB standby current of 2.5mA is met. The SP491 is specified to transmit and receive data at a rate of up to 5 Mbaud. In this example the maximum data rate is limited to 3 Mbaud by the FT232R. Copyright © 2010 Future Technology Devices International Limited 29 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.4 USB to MCU UART Interface Vcc Vcc Ferrite Bead 1 RXD TXD VCC 2 TXD RXD USBDM 3 RTS# CTS# USBDP CTS# RTS# 4 10nF + VCCIO DTR# FT232R 5 NC DSR# RESET# DCD# SHIELD NC RI# OSCI 12MHz GND CBUS0 CLK_IN OSCO OUT Vcc Vcc CBUS1 10K 3V3OUT CBUS2 100nF 4.7uF + A T CBUS3 I/O G G G G E PWREN# N N N N S CBUS4 100nF D D D D T GND GND GND Figure 7.4 USB to MCU UART Interface An example of using the FT232R as a USB to Microcontroller (MCU) UART interface is shown in Figure 7.4. In this application the FT232R uses TXD and RXD for transmission and reception of data, and RTS# / CTS# signals for hardware handshaking. Also in this example CBUS0 has been configured as a 12MHz output to clock the MCU. Optionally, RI# could be connected to another I/O pin on the MCU and used to wake up the USB host controller from suspend mode. If the MCU is handling power management functions, then a CBUS pin can be configured as PWREN# and would also be connected to an I/O pin of the MCU. Copyright © 2010 Future Technology Devices International Limited 30 Microcontroller Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.5 LED Interface Any of the CBUS I/O pins can be configured to drive an LED. The FT232R has 3 configuration options for driving LEDs from the CBUS. These are TXLED#, RXLED#, and TX&RXLED#. Refer to Section 3.5 for configuration options. VCCIO TX RX 270R 270R FT232R TXLED# CBUS[0...4] CBUS[0...4] RXLED# Figure 7.5 Dual LED Configuration An example of using the FT232R to drive LEDs is shown in Figure 7.5. In this application one of the CBUS pins is used to indicate transmission of data (TXLED#) and another is used to indicate receiving data (RXLED#). When data is being transmitted or received the respective pins will drive from tri-state to low in order to provide indication on the LEDs of data transfer. A digital one-shot is used so that even a small percentage of data transfer is visible to the end user. VCCIO LED 270R FT232R TX&RXLED# CBUS[0...4] Figure 7.6 Single LED Configuration Another example of using the FT232R to drive LEDs is shown in Figure 7.6. In this example one of the CBUS pins is used to indicate when data is being transmitted or received by the device (TX&RXLED). In this configuration the FT232R will drive only a single LED. Copyright © 2010 Future Technology Devices International Limited 31 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.6 Using the External Oscillator The FT232R defaults to operating using its own internal oscillator. This requires that the device is powered with VCC(min)=+4.0V. This supply voltage can be taken from the USB VBUS. Applications which require using an external oscillator, VCC= +3.3V, must do so in the following order: 1. When device powered for the very first time, it must have VCC > +4.0V. This supply is available from the USB VBUS supply = +5.0V. 2. The EEPROM must then be programmed to enable external oscillator. This EEPROM modification cannot be done using the FTDI programming utility, MPROG. The EEPROM can only be re- configured from a custom application. Please refer to the following applications note on how to do this: http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_ Osc(FT_000067).pdf 3. The FT232R can then be powered from VCC=+3.3V and an external oscillator. This can be done using a link to switch the VCC supply. The FT232R will fail to operate when the internal oscillator has been disabled, but no external oscillator has been connected. Copyright © 2010 Future Technology Devices International Limited 32 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 8 Internal EEPROM Configuration Following a power-on reset or a USB reset the FT232R will scan its internal EEPROM and read the USB configuration descriptors stored there. The default factory programmed values of the internal EEPROM are shown in Table 8.1. Parameter Value Notes USB Vendor ID (VID) 0403h FTDI default VID (hex) USB Product UD (PID) 6001h FTDI default PID (hex) Serial Number Enabled? Yes A unique serial number is generated and Serial Number See Note programmed into the EEPROM during device final test. Enabling this option will make the device pull down Pull down I/O Pins in USB Disabled on the UART interface lines when in USB suspend Suspend mode (PWREN# is high). Manufacturer Name FTDI Product Description FT232R USB UART Max Bus Power Current 90mA Power Source Bus Powered Device Type FT232R Returns USB 2.0 device description to the host. USB Version 0200 Note: The device is a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). Taking RI# low will wake up the USB host controller Remote Wake Up Enabled from suspend in approximately 20 ms. Enables the high drive level on the UART and CBUS High Current I/Os Disabled I/O pins. Makes the device load the VCP driver interface for Load VCP Driver Enabled the device. Default configuration of CBUS0 – Transmit LED CBUS0 TXLED# drive. CBUS1 RXLED# Default configuration of CBUS1 – Receive LED drive. Default configuration of CBUS2 – Transmit data CBUS2 TXDEN enable for RS485 Default configuration of CBUS3 – Power enable. Low CBUS3 PWREN# after USB enumeration, high during USB suspend mode. Copyright © 2010 Future Technology Devices International Limited 33 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Value Notes Default configuration of CBUS4 – Low during USB CBUS4 SLEEP# suspend mode. Invert TXD Disabled Signal on this pin becomes TXD# if enable. Invert RXD Disabled Signal on this pin becomes RXD# if enable. Invert RTS# Disabled Signal on this pin becomes RTS if enable. Invert CTS# Disabled Signal on this pin becomes CTS if enable. Invert DTR# Disabled Signal on this pin becomes DTR if enable. Invert DSR# Disabled Signal on this pin becomes DSR if enable. Invert DCD# Disabled Signal on this pin becomes DCD if enable. Invert RI# Disabled Signal on this pin becomes RI if enable. Table 8.1 Default Internal EEPROM Configuration The internal EEPROM in the FT232R can be programmed over USB using the FTDI utility program MPROG. MPROG can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). Version 2.8a or later is required for the FT232R chip. Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI support for this service. Copyright © 2010 Future Technology Devices International Limited 34 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9 Package Parameters The FT232R is available in two different packages. The FT232RL is the SSOP-28 option and the FT232RQ is the QFN-32 package option. The solder reflow profile for both packages is described in Section 9.5. 9.1 SSOP-28 Package Dimensions 7.80 + / -0.40 5.30 +/-0.30 1 28 1.02 Typ. 0.05 Min 0.30 +/-0.012 12° Typ 1.25 +/-0.12 0.09 0.25 0° - 8° 0.75 +/-0.20 0.65 +/-0.026 14 15 Figure 9.1 SSOP-28 Package Dimensions The FT232RL is supplied in a RoHS compliant 28 pin SSOP package. The package is lead (Pb) free and uses a „green‟ compound. The package is fully compliant with European Union directive 2002/95/EC. This package is nominally 5.30mm x 10.20mm body (7.80mm x 10.20mm including pins). The pins are on a 0.65 mm pitch. The above mechanical drawing shows the SSOP-28 package. All dimensions are in millimetres. The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This is followed by the revision number. The code XXXXXXXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009. Copyright © 2010 Future Technology Devices International Limited 35 1.75 +/- 0.10 2.00 Max 10.20 +/-0.30 FTDI YYXX-A XXXXXXXXXXXX FT232RL Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.2 QFN-32 Package Dimensions 32 25 1 24 Indicates Pin #1 FTDI (Laser Marked) YYXX-A XXXXXXX 8 FT232RQ 17 9 16 5.000 +/-0.075 Central Heat Sink 9 10 11 12 13 14 15 16 Area 0.150 Max 8 17 0.500 7 18 6 19 5 20 0.250 +/-0.050 4 21 3 22 2 23 1 24 0.200 Min 32 31 30 29 28 27 26 25 Pin #1 ID 3.200 +/-0.100 0.500 +/-0.050 0.900 +/ -0.100 0.200 0.050 Note: The pin #1 ID is connected internally to the device’s central heat sink area . It is recommended to ground the central heat sink area of the device. Dimensions in mm. Figure 9.2 QFN-32 Package Dimensions The FT232RQ is supplied in a RoHS compliant leadless QFN-32 package. The package is lead ( Pb ) free, and uses a „green‟ compound. The package is fully compliant with European Union directive 2002/95/EC. This package is nominally 5.00mm x 5.00mm. The solder pads are on a 0.50mm pitch. The above mechanical drawing shows the QFN-32 package. All dimensions are in millimetres. The centre pad on the base of the FT232RQ is not internally connected, and can be left unconnected, or connected to ground (recommended). The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. The code XXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009. Copyright © 2010 Future Technology Devices International Limited 36 3.200 +/-0.100 5.000 +/-0.075 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.3 QFN-32 Package Typical Pad Layout 2.50 25 0.150 Max 1 0.500 Optional GND Optional GND Connection Connection3.200 +/-0.100 0.30 0.20 2.50 17 0.200 Min 9 0.100 0.500 +/-0.050 Figure 9.3 Typical Pad Layout for QFN-32 Package 9.4 QFN-32 Package Typical Solder Paste Diagram 2.5 +/- 0.0375 2.5 +/- 0.0375 Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package Copyright © 2010 Future Technology Devices International Limited 37 3.200 +/-0.100 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.5 Solder Reflow Profile The FT232R is supplied in Pb free 28 LD SSOP and QFN-32 packages. The recommended solder reflow profile for both package options is shown in Figure 9.5. tp Tp Critical Zone: when Ramp Up T is in the range TL to Tp TL tL TS Max Ramp Down TS Min tS Preheat 25 T = 25º C to TP Time, t (seconds) Figure 9.5 FT232R Solder Reflow Profile The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for both a completely Pb free solder process (i.e. the FT232R is used with Pb free solder), and for a non-Pb free solder process (i.e. the FT232R is used with non-Pb free solder). Profile Feature Pb Free Solder Process Non-Pb Free Solder Process Average Ramp Up Rate (Ts to Tp) 3°C / second Max. 3°C / Second Max. Preheat - Temperature Min (Ts Min.) 150°C 100°C - Temperature Max (Ts Max.) 200°C 150°C - Time (ts Min to ts Max) 60 to 120 seconds 60 to 120 seconds Time Maintained Above Critical Temperature TL: 217°C 183°C - Temperature (TL) 60 to 150 seconds 60 to 150 seconds - Time (tL) Peak Temperature (Tp) 260°C 240°C Time within 5°C of actual Peak Temperature 20 to 40 seconds 20 to 40 seconds (tp) Ramp Down Rate 6°C / second Max. 6°C / second Max. Time for T= 25°C to Peak Temperature, Tp 8 minutes Max. 6 minutes Max. Table 9.1 Reflow Profile Parameter Values Copyright © 2010 Future Technology Devices International Limited 38 Temperature, T (Degrees C) Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 10 Contact Information Head Office – Glasgow, UK Future Technology Devices International Limited Unit 1, 2 Seaward Place Centurion Business Park Glasgow, G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 E-mail (Sales) sales1@ftdichip.com E-mail (Support) support1@ftdichip.com E-mail (General Enquiries) admin1@ftdichip.com Web Site URL http://www.ftdichip.com Web Shop URL http://www.ftdichip.com Branch Office – Taipei, Taiwan Future Technology Devices International Limited (Taiwan) 2F, No 516, Sec. 1 NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8791 3570 Fax: +886 (0) 2 8791 3576 E-mail (Sales) tw.sales1@ftdichip.com E-mail (Support) tw.support1@ftdichip.com E-mail (General Enquiries) tw.admin1@ftdichip.com Web Site URL http://www.ftdichip.com Branch Office – Hillsboro, Oregon, USA Future Technology Devices International Limited (USA) 7235 NW Evergreen Parkway, Suite 600 Hillsboro, OR 97123-5803 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-Mail (Sales) us.sales@ftdichip.com E-Mail (Support) us.admin@ftdichip.com Web Site URL http://www.ftdichip.com Branch Office – Shanghai, China Future Technology Devices International Limited (China) Room 408, 317 Xianxia Road, ChangNing District, ShangHai, China Tel: +86 (21) 62351596 Fax: +86(21) 62351595 E-Mail (Sales): cn.sales@ftdichip.com E-Mail (Support): cn.support@ftdichip.com E-Mail (General Enquiries): cn.admin1@ftdichip.com Web Site URL: http://www.ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Copyright © 2010 Future Technology Devices International Limited 39 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix A – References Useful Application Notes http://www.ftdichip.com/Documents/AppNotes/AN232R-01_FT232RBitBangModes.pdf http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf http://www.ftdichip.com/Documents/AppNotes/AN232R-02_FT232RChipID.pdf http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_ 000067).pdf http://www.ftdichip.com/Resources/Utilities/AN_126_User_Guide_For_FT232_Factory%20test%20utility. pdf http://www.ftdichip.com/Documents/AppNotes/AN232B-05_BaudRates.pdf http://www.ftdichip.com/Documents/InstallGuides.htm Copyright © 2010 Future Technology Devices International Limited 40 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix B - List of Figures and Tables List of Figures Figure 2.1 FT232R Block Diagram ................................................................................................... 4 Figure 3.1 SSOP Package Pin Out and Schematic Symbol .......................................................... 7 Figure 3.2 QFN-32 Package Pin Out and schematic symbol .............................................................. 10 Figure 6.1 Bus Powered Configuration ........................................................................................... 23 Figure 6.2 Self Powered Configuration ........................................................................................... 24 Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply .................................... 26 Figure 7.1 Application Example showing USB to RS232 Converter ..................................................... 27 Figure 7.2 Application Example Showing USB to RS485 Converter .................................................... 28 Figure 7.3 USB to RS422 Converter Configuration ........................................................................... 29 Figure 7.4 USB to MCU UART Interface .......................................................................................... 30 Figure 7.5 Dual LED Configuration ................................................................................................ 31 Figure 7.6 Single LED Configuration .............................................................................................. 31 Figure 9.1 SSOP-28 Package Dimensions ....................................................................................... 35 Figure 9.2 QFN-32 Package Dimensions ......................................................................................... 36 Figure 9.3 Typical Pad Layout for QFN-32 Package .......................................................................... 37 Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package ........................................................... 37 Figure 9.5 FT232R Solder Reflow Profile ........................................................................................ 38 List of Tables Table 3.1 USB Interface Group ....................................................................................................... 7 Table 3.2 Power and Ground Group ................................................................................................. 8 Table 3.3 Miscellaneous Signal Group .............................................................................................. 8 Table 3.4 UART Interface and CUSB Group (see note 3) .................................................................... 9 Table 3.5 USB Interface Group ..................................................................................................... 10 Table 3.6 Power and Ground Group ............................................................................................... 11 Table 3.7 Miscellaneous Signal Group ............................................................................................ 11 Table 3.8 UART Interface and CBUS Group (see note 3) .................................................................. 12 Table 3.9 CBUS Configuration Control ........................................................................................... 13 Table 5.1 Absolute Maximum Ratings ............................................................................................ 17 Table 5.2 Operating Voltage and Current ....................................................................................... 18 Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) .................. 18 Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) .................. 18 Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) .................. 19 Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) .................. 19 Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) ......................... 19 Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) ......................... 19 Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) ......................... 20 Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ....................... 20 Copyright © 2010 Future Technology Devices International Limited 41 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Table 5.11 RESET# and TEST Pin Characteristics ............................................................................ 20 Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics ................................................................. 21 Table 5.13 EEPROM Characteristics ............................................................................................... 21 Table 5.14 Internal Clock Characteristics ....................................................................................... 21 Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 ................................................................. 22 Table 8.1 Default Internal EEPROM Configuration ............................................................................ 34 Table 9.1 Reflow Profile Parameter Values ..................................................................................... 38 Copyright © 2010 Future Technology Devices International Limited 42 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix C - Revision History Document Title: USB UART IC FT232R Document Reference No.: FT_000053 Clearance No.: FTDI# 38 Product Page: http://www.ftdichip.com/FTProducts.htm Document Feedback: Send Feedback Version 0.90 Initial Datasheet Created August 2005 Version 0.96 Revised Pre-release datasheet October 2005 Version 1.00 Full datasheet released December 2005 Version 1.02 Minor revisions to datasheet December 2005 Version 1.03 Manufacturer ID added to default EEPROM configuration; Buffer sizes added January 2006 Version 1.04 QFN-32 Pad layout and solder paste diagrams added January 2006 Version 2.00 Reformatted, updated package info, added notes for 3.3V operation; June 2008 Part numbers, TID; added UART and CBUS characteristics for +1.8V; Corrected RESET#; Added MTTF data; Corrected the input switching threshold and input hysteresis values for VCCIO=5V Version 2.01 Corrected pin-out number in table3.2 for GND pin18. Improved graphics on some Figures. Add packing details. Changed USB suspend current spec from 500uA to 2.5mA Corrected Figure 9.2 QFN dimensions. August 2008 Version 2.02 Corrected Tape and Reel quantities. Added comment “PWREN# should be used with a 10kΩ resistor pull up”. Replaced TXDEN# with TXDEN since it is active high in various places. Added lot number to the device markings. Added 3V3 regulator output tolerance. Clarified VCC operation and added section headed “Using an external Oscillator” Updated company contact information. April 2009 Version 2.03 Corrected the RX/TX buffer definitions to be relative to the USB interface June 2009 Version 2.04 Additional dimensions added to QFN solder profile June 2009 Version 2.05 Modified package dimensions to 5.0 x 5.0 +/-0.075mm. December 2009 and Solder paste diagram to 2.50 x 2.50 +/-0.0375mm Added Windows 7 32, 64 bit driver support Added FT_PROG utility references Added Appendix A-references.Figure 2.1 updated. Updated USB-IF TID for Rev B Version 2.06 Updated section 6.2, Figure 6.2 and the note, May 2010 Updated section 5.3, Table 5.13, EEPROM data retention time Version 2.07 Added USB Certification Logos July 2010 Version 2.08 Updated USB-IF TID for Rev C April 2011 Version 2.09 Corrected Rev C TID number April 2011 Version 2.10 Table 3.9, added clock output frequency within ±0.7% March 2012 Edited Table 3.9, TXLED# and TXLED# Description Added feedback links Copyright © 2010 Future Technology Devices International Limited 43 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT standard level field-effect power transistor in a plastic envelope using VDS Drain-source voltage 55 V ’trench’ technology. The device ID Drain current (DC) 49 A features very low on-state resistance Ptot Total power dissipation 110 W and has integral zener diodes giving Tj Junction temperature 175 ˚C ESD protection up to 2kV. It is RDS(ON) Drain-source on-state 22 mΩ intended for use in switched mode resistance VGS = 10 V power supplies and general purpose switching applications. PINNING - TO220AB PIN CONFIGURATION SYMBOL PIN DESCRIPTION d tab 1 gate 2 drain g 3 source tab drain 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS Drain-source voltage - - 55 V VDGR Drain-gate voltage RGS = 20 kΩ - 55 V ±VGS Gate-source voltage - - 20 V ID Drain current (DC) Tmb = 25 ˚C - 49 A ID Drain current (DC) Tmb = 100 ˚C - 35 A IDM Drain current (pulse peak value) Tmb = 25 ˚C - 160 A Ptot Total power dissipation Tmb = 25 ˚C - 110 W Tstg, Tj Storage & operating temperature - - 55 175 ˚C ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VC Electrostatic discharge capacitor Human body model - 2 kV voltage, all pins (100 pF, 1.5 kΩ) THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT Rth j-mb Thermal resistance junction to - - 1.4 K/W mounting base Rth j-a Thermal resistance junction to in free air 60 - K/W ambient February 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V voltage Tj = -55˚C 50 - - V VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2.0 3.0 4.0 V Tj = 175˚C 1.0 - - V Tj = -55˚C - - 4.4 IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA Tj = 175˚C - - 500 µA IGSS Gate source leakage current VGS = ±10 V; VDS = 0 V - 0.04 1 µA Tj = 175˚C - - 20 µA ±V(BR)GSS Gate source breakdown voltage IG = ±1 mA; 16 - - V RDS(ON) Drain-source on-state VGS = 10 V; ID = 25 A - 15 22 mΩ resistance Tj = 175˚C - - 42 mΩ DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT gfs Forward transconductance VDS = 25 V; ID = 25 A 6 - - S Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1350 1800 pF Coss Output capacitance - 330 400 pF Crss Feedback capacitance - 155 215 pF Qg Total gate charge VDD = 44 V; ID = 50 A; VGS = 10 V - - 62 nC Qgs Gate-cource charge - - 15 nC Qgd Gate-drain (miller) charge - - 26 nC td on Turn-on delay time VDD = 30 V; ID = 25 A; - 18 26 ns tr Turn-on rise time VGS = 10 V; RG = 10 Ω - 50 75 ns td off Turn-off delay time Resistive load - 40 50 ns tf Turn-off fall time - 30 40 ns Ld Internal drain inductance Measured from contact screw on - 3.5 - nH tab to centre of die Ld Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH from package to centre of die Ls Internal source inductance Measured from source lead 6 mm - 7.5 - nH from package to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IDR Continuous reverse drain - - 49 A current IDRM Pulsed reverse drain current - - 160 A VSD Diode forward voltage IF = 25 A; VGS = 0 V - 0.95 1.2 V IF = 40 A; VGS = 0 V - 1.0 - trr Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs; - 47 - ns Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.15 - µC February 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT WDSS Drain-source non-repetitive ID = 45 A; VDD ≤ 25 V; - - 110 mJ unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C energy PD% Normalised Power Derating 1000 120 110 ID/A 100 90 tp =RDS(ON) =VDS/ID 80 100 1 us 70 10us 60 100 us 50 40 DC 10 1 ms 30 20 10ms 10 100ms 0 0 20 40 60 80 100 120 140 160 180 1 Tmb / C 1 10 VDS/V 100 Fig.1. Normalised power dissipation. Fig.3. Safe operating area. Tmb = 25 ˚C PD% = 100⋅PD/PD 25 ˚C = f(Tmb) ID & IDM = f(VDS); IDM single pulse; parameter tp ID% Normalised Current Derating Zth/(K/W) 120 10 110 100 90 1 0.5 80 70 0.2 60 0.10.1 0.05 50 P tp D = tpD 0.02 T 40 30 0.01 0 T t 20 10 0 0 20 40 60 80 100 120 140 160 180 0.001 1E-06 0.0001 0.01 1 100 Tmb / C t/s Fig.2. Normalised continuous drain current. Fig.4. Transient thermal impedance. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V Zth j-mb = f(t); parameter D = tp/T February 1999 3 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor 100 30 16 9 VGS/V = ID/A gfs/S8.0 10 8.5 25 80 7.5 20 60 7.0 15 6.5 40 10 6.0 20 5.5 5 5.0 4.5 0 0 2 4 6 8 10 4.0 0 0 20 40 60 80 100 VDS/V ID/A Fig.5. Typical output characteristics, Tj = 25 ˚C. Fig.8. Typical transconductance, Tj = 25 ˚C. ID = f(VDS); parameter VGS gfs = f(ID); conditions: VDS = 25 V RDS(ON)/mOhm 40 a BUK959-60 Rds(on) normlised to 25degC VGS/V = 2.5 35 6 2 30 6.5 7 25 1.5 8 9 20 10 1 15 0.5 10 0 10 20 30 40 50 60 70 80 90 -100 -50 0 50 100 150 200 ID/A Tmb / degC Fig.6. Typical on-state resistance, Tj = 25 ˚C. Fig.9. Normalised drain-source on-state resistance. RDS(ON) = f(ID); parameter VGS a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 10 V 100 VGS(TO) / V BUK759-60 5 ID/A max. 80 4 typ. 60 3 min. 40 2 20 1 Tj/C = 175 25 0 0 0 2 4 6 8 10 12 -100 -50 0 50 100 150 200 VGS/V Tj / C Fig.7. Typical transfer characteristics. Fig.10. Gate threshold voltage. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS February 1999 4 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor Sub-Threshold Conduction 100 1E-01 IF/A 80 1E-02 2% 1E-03 typ 98% 60 Tj/C = 175 25 40 1E-04 20 1E-05 0 1E-06 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1 2 3 4 5 VSDS/V Fig.11. Sub-threshold drain current. Fig.14. Typical reverse diode current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 2.5 WDSS% 120 110 2 100 90 80 1.5 70 Ciss 60 50 1 40 30 .5 20 Coss 10 Crss 0 0 20 40 60 80 100 120 140 160 180 0.01 0.1 1 VDS/V 10 100 Tmb / C Fig.12. Typical capacitances, Ciss, Coss, Crss. Fig.15. Normalised avalanche energy rating. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz WDSS% = f(Tmb); conditions: ID = 49 A 12 VGS/V VDD 10 + L VDS = 14V 8 VDS VDS = 44V - 6 VGS -ID/100 0 T.U.T.4 R 01 2 RGS shunt 0 0 10 20 QG/nC 30 40 50 Fig.16. Avalanche energy test circuit. Fig.13. Typical turn-on gate-charge characteristics. 2 VGS = f(QG); conditions: ID = 50 A; parameter V WDSS = 0.5 ⋅ LIDS D ⋅ BVDSS/(BVDSS − VDD) February 1999 5 Rev 1.000 Thousands pF Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor + VDD RD VDS - VGS RG 0 T.U.T. Fig.17. Switching test circuit. February 1999 6 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor MECHANICAL DATA Dimensions in mm 4,5 Net Mass: 2 g max 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 0,6 2,54 2,54 2,4 Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". February 1999 7 Rev 1.000 Philips Semiconductors Product specification N-channel enhancement mode IRFZ44N TrenchMOSTM transistor DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. February 1999 8 Rev 1.000 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components. User’s Guide GDM12864HLCM (Liquid Crystal Display Module) For product support, contact XIAMEN OCULAR OPTICS CO.,LTD. 厦门高卓立光电有限公司 South2/F.,Guangxia Building Torch Hi-tech Industrial Development Area Xiamen, China 36100 中国厦门火炬高技术产业开发区光厦楼南二楼 Tel: 86-592-5650516 Fax: 86-592-5650695 CONTENTS Mechanical diagram Absolute maximum ratings Interface pin connections Optical characteristics Electrical characteristics KS0107B KS0108B Write or read cycle Timing characteristics Block diagram Display commands Reliability and lift time Operating Principles & Methods XIAMEN OCULAR OPTICS CO., LTD. 2 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 Ø Mechanical diagram Ø Absolute maximum ratings Item Symbol Min. Max. Unit Supply voltage for logic Vdd - Vss 0 6.5 V Input voltage Vin 0 Vdd Operating temperature range T0p -20 70 Storage temperature range Tst -25 75 Ø Interface pin connections Pin No. Symbol Level Description 1 Vdd 5.0V Supply voltage for logic and LCD (+) 2 Vss 0V Ground 3 V0 - Operating voltage for LCD (variable) 4~11 DB0~DB7 H/L Data bit 0~7 12 CS2 L Chip select signal for IC2 13 CS1 L Chip select signal for IC1 14 /RES L Reset signal 15 R/W H/L H: read (MUP< module),L: write (MPU >module) 16 D/I H/L H: data, L: instruction code 17 E H, HL Chip enable signal 18 VEE - Operating voltage for LCD (variable) 19 A 4.2V Backlight power supply 20 K 0V Backlight power supply XIAMEN OCULAR OPTICS CO., LTD. 3 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 Ø Optical characteristics STN Type display module (Ta=25 , Vdd=5.0V) Item Symbol Condition Min. Typ. Max. Unit -60 - 35 Viewing angle Cr 2 deg ф -40 - 40 Contrast ratio (rise) Cr - 6 - Response time (fall) Tr - - 150 250 ms Tr - - 150 250 ms Ø Electrical characteristics Item Symbol Condition Standard value Unit Min. Typ. Max. Logic Vdd - Vss - 4.75 5.0 5.25 Supply voltage for V LCD Vdd-V0 - - 9.5 - Logic Idd - - 2.5 - Supply current for mA LCD Iee - - 1.0 - - - - - Operating voltage for LCD Vdd-v0 (Recommended) 25 - 9.5 - - - - - H: level Vih High level 0.7Vdd - Vdd V Input voltage L: Level Vil Low level 0 - 0.3Vdd Electrical Absolute Maximum Ratings (KS0107B) Parameter Symbol Rating Unit Note Operating voltage VDD -0.3 ~ +7.0 V *1 Supply voltage VEE VDD-19.0 ~ VDD+0.3 V *4 Driver supply voltage VB -0.3 ~ VDD+0.3 V *1,2 VLCD VEE-0.3 ~ VDD+0.3 V *3,4 *Notes: *1. Based on VSS = 0V *2. Applies to input terminals and I/O terminals at high impedance. (Except V0L, V1L, V4L, and V5L) *3. Applies to V0L, V1L, V4L, and V5L. *4. Voltage level: VDD V0 V1 V2 V3 V4 V5 VEE XIAMEN OCULAR OPTICS CO., LTD. 4 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 DC Electrical Characteristics (KS0107B) (VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85 ) Item Symbol Condition Min. Typ. Max. Unit Note Operating voltage VDD - 4.5 - 5.5 V - 0.7 - V Input voltage IH VDD DD *1 VIL - VSS - 0.3VDD V VOH IOH= -0.4mA VDD-0.4 - - output voltage *2 VOL IOL= 0.4mA - - 0.4 Input leakage current ILKG VIN= VDD ~ VSS -1.0 - +1.0 µA *1 fosc Rf=47k 2% 315 450 585 OSC Frequency kHz Cf=20pF 5% On Resistance RONS VDD-VEE=17V - - 1.5 k (Vdiv-Ci) Load current 150µA IDD1 Master mode - - 1.0 *3 Operating current 1/128 Duty IDD2 Master mode - - 0.2 mA *4 1/128 Duty IEE Master mode - - 0.1 Supply Current *5 1/128 Duty Operating fop1 Master mode 50 - 600 External Duty kHz Frequency fop2 Slave mode 0.5 - 1500 Notes *1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M, and CL2 in the input state. *2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M, and CL2 in the output state. *3. This value is specified about current flowing through VSS. Internal oscillation circuit: Rf=47k , cf=20pF Each terminals of DS1, DS2, FS, SHL, and MS is connected to VDD and out is no load. *4. This value is specified about current flowing through VSS. Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD,MS is connected to VSS and CL2, M, DIO1 is external clock. *5. This value is specified about current flowing through VEE, Don’t connect to VLCD (V1~V5). XIAMEN OCULAR OPTICS CO., LTD. 5 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 Electrical Absolute Maximum Ratings (KS0108B) Parameter Symbol Rating Unit Note Operating voltage VDD -0.3 ~ +7.0 V *1 Supply voltage VEE VDD-19.0 ~ VDD+0.3 V *4 Driver supply voltage VB -0.3 ~ VDD+0.3 V *1,3 VLCD VEE-0.3 ~ VDD+0.3 V *2 *Notes: *1. Based on VSS = 0V *2. Applies the same supply voltage to VEE. VLCD=VDD-VEE. *3. Applies to M, FRM, CLK1, CLK2, CL, RESETB, ADC, CS1B, CS2B, CS3, E, R/W, RS and DB0~DB7. *4. Applies V0L, V2L, V3L and V5L. Voltage level: VDD V0 V1 V2 V3 V4 V5 VEE DC Electrical Characteristics (KS0108B) (VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85 ) Item Symbol Condition Min. Typ. Max. Unit Note Operating voltage VDD - 4.5 - 5.5 V Input High voltage IH1 - 0.7VDD - VDD *1 VIH2 - 2.0 - VDD *2 VIL1 - 0 - 0.3V V *1Input Low voltage DD VIL2 - 0 - 0.8 *2 Output High Voltage VOH IOH= -0.2mA 2.4 - - *3 Output Low Voltage VOL IOL= 1.6mA - - 0.4 *3 Input leakage current ILKG VIN= VSS ~ VDD -1.0 - +1.0 µA *4 Three-state (OFF) ITSL VIN= VSS ~ VDD -5.0 5.0 - *5 Input Current Driver Input leakage IDIL VIN= VEE ~ VDD -2.0 2.0 *6 current On Resistance RONS VDD-VEE=15V - 7.5 - k *8 (Vdiv-Ci) Load current 100µA IDD1 During Display - - 0.1 *7 Operating current IDD2 During Access - 0.5 mA - *7 Access Cycle=1MHz Notes *1. CL, FRM, M, RSTB, CLK1, CLK2 *2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7 *3. DB0~DB7 *4. Except DB0~DB7 *5. DB0~DB7 at high impedance *6. V0, V1, V3, V3, V4, V5 *7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load *8. VDD-VEE=15.5V V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L XIAMEN OCULAR OPTICS CO., LTD. 6 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 Ø Write or read cycle Characteristic Symbol Min. Typ. Max. Unit E cycle Tc 1000 - - ns E high level width Twh 450 - - ns E low level width Twl 450 - - ns E rise time Tr - - 25 ns E fall time Tf - - 25 ns Address set-up time Tasu 140 - - ns Address hold time Tah 10 - - ns Data set-up time Tdsu 200 - - ns Data delay time Td - - 320 ns Data hold time (write) Tdhw 10 - - ns Data hold time (read) Tdhr 20 - - ns ² Write timing tC t E W L tW H t R tF t AH R/W tA S U t A S U t AH CS1,CS2 CS,RS tDSU tDHW D B 0 ~ D B 7 MPU Write t iming XIAMEN OCULAR OPTICS CO., LTD. 7 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 ² Read timing tC tWL E tWH tR tF R/W tASU tAH t t ASU AH CS1,CS2 CS,RS tD tWH DB0~DB7 MPU Read timing XIAMEN OCULAR OPTICS CO., LTD. 8 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 ² Block diagram IC3 COM 1~64 LCD PANEL SEG1~64 SEG65~128 V0 VDD VSS IC1 IC2 IC4 VEE 5 8 3 5 8 3 DB0~DB7 8 /RET CS R/W E RS 3 A LED BACKLIGHT MODULE K +5V VDD LCM Vo VR VEE VSS GND VDD-Vo:LCD DRIVING VOLTAGE VR:10K~20K *Note 1/64 duty, 1/9 bias VDD>V1>V2>V3>V4>V5>VEE XIAMEN OCULAR OPTICS CO., LTD. 9 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 ² Display Control Instruction The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the display control. The following table shows various instructions. Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Read Display Reads data (DB[7:0])from 1 1 Read data Data display data RAM to the data bus. Writes data (DB[7:0]) into Write Display display data RAM. After 1 0 Write data Data writing instruction, Y address is incriminated by 1 automatically Reads the internal status BUSY 0: Ready 1: In operation ON/ Re- Status Read 0 1 Busy 0 0 0 0 0 ON/OFF OFF set 0: Display ON 1: Display OFF RESET 0: Normal 1: Reset Set Address Sets the Y address in the Y 0 0 0 1 Y address (0~63) (Y address) address counter Set Display Indicates the display data 0 0 1 1 Display start line (0~63) Start Line RAM displayed at the top of the screen. Set Address Sets the X address at the X 0 0 1 0 1 1 1 Page (0~7) (X address) address register. Controls the display ON or OFF. The internal status Display On/off 0 0 0 0 1 1 1 1 1 0/1 and the DDRAM data is not affected. 0: OFF, 1: ON 1. Display On/Off The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D=0, it remains in the display data RAM. Therefore, you can make it appear by changing D=0 into D=1. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 1 1 D 2. Set Address (Y Address) Y address (AC0~AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 XIAMEN OCULAR OPTICS CO., LTD. 10 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 3. Set Page (X Address) X address (AC0~AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 1 AC2 AC1 AC0 4. Display Start Line (Z Address) Z address (AC0~AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others (1/32~1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0 5. Status Read RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 BUSY 0 ON/OFF RESET 0 0 0 0 l BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. l ON/OFF When ON/OFF is 1, the display is on. When ON/OFF is 0, the display is off. l RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition. 6. Write Display Data Writes data (D0~D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 7. Read Display Data Reads data (D0~D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 XIAMEN OCULAR OPTICS CO., LTD. 11 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 ² Operating principles & methods 1. I/O Buffer Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS!B-CS3. 2. Input register Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. 3. Output register Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W=H , RS=L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. RS R/W Function L L Instruction H Status read (busy check) L Data write (from input register to display data RAM ) H H Data read (from display data RAM to output register) 4. Reset The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. 1. Display off 2. Display start line register become set by 0. (Z-address 0) While RSTB is low, No instruction except status read can by accepted. Therefore, execute other instructions after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction. The conditions of power supply at initial power up are shown in table 1. Table 1. Power Supply Initial Conditions Item Symbol Min Typ Max Unit Reset Time tRS 1.0 - - us Rise Time tR - - 200 ns 4.5[V] VDD tRS tR RSTB 0.7VDD 0.3VDD XIAMEN OCULAR OPTICS CO., LTD. 12 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 5. Busy flag Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating . When busy flag is low, KS0108B can accept the data or instruction. DB7indicates busy flag of the KS0108B. E Busy Flag T Busy 1/fCLK Y-address 0: S1~Y address 63: S64 ADC=L => Y-address 0: S64~Yaddress 63: S1 ADC terminal connect the VDD or VSS. 10. Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0.5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen. XIAMEN OCULAR OPTICS CO., LTD. 13 SOUTH2/F, GUANGXIA BUILDING, TORCH HIGH-TECH DEVELOPMENT ARER, XIAMEN 361006.P.R.CHINA TEL: 86-592-5650516 FAX: 86-592-5650695 August 2012 LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Features General Description • Output Current up to 1A The LM78XX series of three terminal positive regulators • Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24 are available in the TO-220 package and with several • Thermal Overload Protection fixed output voltages, making them useful in a wide • Short Circuit Protection range of applications. Each type employs internal current • Output Transistor Safe Operating Area Protection limiting, thermal shut down and safe operating area pro- tection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external com- ponents to obtain adjustable voltages and currents. Ordering Information Product Number Output Voltage Tolerance Package Operating Temperature LM7805CT ±4% TO-220 (Single Gauge) -40C to +125C LM7806CT LM7808CT LM7809CT LM7810CT LM7812CT LM7815CT LM7818CT LM7824CT LM7805ACT ±2% 0C to +125C LM7806ACT LM7808ACT LM7809ACT LM7810ACT LM7812ACT LM7815ACT LM7818ACT LM7824ACT © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX/LM78XXA Rev. 1.2 1 LM78XX/LM78XXA — 3-Terminal 1A Positive Voltage Regulator Block Diagram Input Series Pass Output Element 1 3 Current SOA Generator Protection Starting Reference Error Circuit Voltage Amplifier Thermal Protection GND 2 Figure 1. Pin Assignment TO-220 (Single Gauge) GND 1. Input 1 2. GND 3. Output Figure 2. Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications. Symbol Parameter Value Unit VI Input Voltage VO = 5V to 18V 35 V VO = 24V 40 V RθJC Thermal Resistance Junction-Cases (TO-220) 5 °C/W RθJA Thermal Resistance Junction-Air (TO-220) 65 °C/W TOPR Operating Temperature LM78xx -40 to +125 °C Range LM78xxA 0 to +125 TSTG Storage Temperature Range -65 to +150 °C LM78XX/LM78XXA Rev. 1.2 2 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7805) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 10V, CI = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 4.8 5.0 5.2 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 4.75 5.0 5.25 VI = 7V to 20V Regline Line Regulation(1) TJ = +25°C VO = 7V to 25V – 4.0 100 mV VI = 8V to 12V – 1.6 50.0 Regload Load Regulation(1) TJ = +25°C IO = 5mA to 1.5A – 9.0 100 mV IO = 250mA to 750mA – 4.0 50.0 IQ Quiescent Current TJ = +25°C – 5.0 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – 0.03 0.5 mA VI = 7V to 25V – 0.3 1.3 ∆VO/∆T Output Voltage Drift(2) IO = 5mA – -0.8 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 42.0 – µV/VO RR Ripple Rejection(2) f = 120Hz, VO = 8V to 18V 62.0 73.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (2) f = 1kHz – 15.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 230 – mA IPK Peak Current (2) TJ = +25°C – 2.2 – A Notes: 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 2. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 3 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7806) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 11V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min Typ. Max. Unit VO Output Voltage TJ = +25°C 5.75 6.0 6.25 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 5.7 6.0 6.3 VI = 8.0V to 21V Regline Line Regulation(3) TJ = +25°C VI = 8V to 25V – 5.0 120 mV VI = 9V to 13V – 1.5 60.0 Regload Load Regulation(3) TJ = +25°C IO = 5mA to 1.5A – 9.0 120 mV IO = 250mA to 750mA – 3.0 60.0 IQ Quiescent Current TJ = +25°C – 5.0 8.0 mA ∆IQ Quiescent Current IO = 5mA to 1A – – 0.5 mA Change VI = 8V to 25V – – 1.3 ∆VO/∆T Output Voltage Drift(4) IO = 5mA – -0.8 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 45.0 – µV/VO RR Ripple Rejection(4) f = 120Hz, VO = 8V to 18V 62.0 73.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (4) f = 1kHz – 19.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA I Peak Current(4)PK TJ = +25°C – 2.2 – A Notes: 3. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 4. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 4 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7808) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 14V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 7.7 8.0 8.3 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 7.6 8.0 8.4 VI = 10.5V to 23V Regline Line Regulation(5) TJ = +25°C VI = 10.5V to 25V – 5.0 160 mV VI = 11.5V to 17V – 2.0 80.0 Regload Load Regulation(5) TJ = +25°C IO = 5mA to 1.5A – 10.0 160 mV IO = 250mA to 750mA – 5.0 80.0 IQ Quiescent Current TJ = +25°C – 5.0 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – 0.05 0.5 mA VI = 10.5V to 25V – 0.5 1.0 ∆VO/∆T Output Voltage Drift(6) IO = 5mA – -0.8 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 52.0 – µV/VO RR Ripple Rejection(6) f = 120Hz, VO = 11.5V to 21.5V 56.0 73.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (6) f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 230 – mA IPK Peak Current (6) TJ = +25°C – 2.2 – A Notes: 5. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 6. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 5 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7809) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 15V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 8.65 9.0 9.35 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 8.6 9.0 9.4 VI = 11.5V to 24V Regline Line Regulation(7) TJ = +25°C VI = 11.5V to 25V – 6.0 180 mV VI = 12V to 17V – 2.0 90.0 Regload Load Regulation(7) TJ = +25°C IO = 5mA to 1.5A – 12.0 180 mV IO = 250mA to 750mA – 4.0 90.0 IQ Quiescent Current TJ = +25°C – 5.0 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 11.5V to 26V – – 1.3 ∆VO/∆T Output Voltage Drift(8) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 58.0 – µV/VO RR Ripple Rejection(8) f = 120Hz, VO = 13V to 23V 56.0 71.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (8) f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (8) TJ = +25°C – 2.2 – A Notes: 7. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 8. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 6 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7810) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 16V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 9.6 10.0 10.4 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 9.5 10.0 10.5 VI = 12.5V to 25V Regline Line Regulation(9) TJ = +25°C VI = 12.5V to 25V – 10.0 200 mV VI = 13V to 25V – 3.0 100 Regload Load Regulation(9) TJ = +25°C IO = 5mA to 1.5A – 12.0 200 mV IO = 250mA to 750mA – 4.0 400 IQ Quiescent Current TJ = +25°C – 5.1 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 12.5V to 29V – – 1.0 ∆VO/∆T Output Voltage Drift(10) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 58.0 – µV/VO RR Ripple Rejection(10) f = 120Hz, VO = 13V to 23V 56.0 71.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance(10) f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current(10) TJ = +25°C – 2.2 – A Notes: 9. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 10. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 7 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7812) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 19V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 11.5 12.0 12.5 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 11.4 12.0 12.6 VI = 14.5V to 27V Regline Line Regulation(11) TJ = +25°C VI = 14.5V to 30V – 10.0 240 mV VI = 16V to 22V – 3.0 120 Regload Load Regulation(11) TJ = +25°C IO = 5mA to 1.5A – 11.0 240 mV IO = 250mA to 750mA – 5.0 120 IQ Quiescent Current TJ = +25°C – 5.1 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – 0.1 0.5 mA VI = 14.5V to 30V – 0.5 1.0 ∆VO/∆T Output Voltage Drift(12) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 76.0 – µV/VO RR Ripple Rejection(12) f = 120Hz, VI = 15V to 25V 55.0 71.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (12) f = 1kHz – 18.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 230 – mA IPK Peak Current (12) TJ = +25°C – 2.2 – A Notes: 11. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 12. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 8 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7815) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 23V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 14.4 15.0 15.6 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 14.25 15.0 15.75 VI = 17.5V to 30V Regline Line Regulation(13) TJ = +25°C VI = 17.5V to 30V – 11.0 300 mV VI = 20V to 26V – 3.0 150 Regload Load Regulation(13) TJ = +25°C IO = 5mA to 1.5A – 12.0 300 mV IO = 250mA to 750mA – 4.0 150 IQ Quiescent Current TJ = +25°C – 5.2 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 17.5V to 30V – – 1.0 ∆VO/∆T Output Voltage Drift(14) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 90.0 – µV/VO RR Ripple Rejection(14) f = 120Hz, VI = 18.5V to 28.5V 54.0 70.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (14) f = 1kHz – 19.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (14) TJ = +25°C – 2.2 – A Notes: 13. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 14. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 9 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7818) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 27V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 17.3 18.0 18.7 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 17.1 18.0 18.9 VI = 21V to 33V Regline Line Regulation(15) TJ = +25°C VI = 21V to 33V – 15.0 360 mV VI = 24V to 30V – 5.0 180 Regload Load Regulation(15) TJ = +25°C IO = 5mA to 1.5A – 15.0 360 mV IO = 250mA to 750mA – 5.0 180 IQ Quiescent Current TJ = +25°C – 5.2 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 21V to 33V – – 1.0 ∆VO/∆T Output Voltage Drift(16) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 110 – µV/VO RR Ripple Rejection(16) f = 120Hz, VI = 22V to 32V 53.0 69.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (16) f = 1kHz – 22.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA I Peak Current(16)PK TJ = +25°C – 2.2 – A Notes: 15. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 16. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 10 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7824) (Continued) Refer to the test circuits. -40°C < TJ < 125°C, IO = 500mA, VI = 33V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 23.0 24.0 25.0 V 5mA ≤ IO ≤ 1A, PO ≤ 15W, 22.8 24.0 25.25 VI = 27V to 38V Regline Line Regulation(17) TJ = +25°C VI = 27V to 38V – 17.0 480 mV VI = 30V to 36V – 6.0 240 Regload Load Regulation(17) TJ = +25°C IO = 5mA to 1.5A – 15.0 480 mV IO = 250mA to 750mA – 5.0 240 IQ Quiescent Current TJ = +25°C – 5.2 8.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – 0.1 0.5 mA VI = 27V to 38V – 0.5 1.0 ∆VO/∆T Output Voltage Drift(18) IO = 5mA – -1.5 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 60.0 – µV/VO RR Ripple Rejection(18) f = 120Hz, VI = 28V to 38V 50.0 67.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance(18) f = 1kHz – 28.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 230 – mA I Peak Current(18)PK TJ = +25°C – 2.2 – A Notes: 17. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 18. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 11 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7805A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 10V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 4.9 5.0 5.1 V IO = 5mA to 1A, PO ≤ 15W, 4.8 5.0 5.2 VI = 7.5V to 20V Regline Line Regulation(19) VI = 7.5V to 25V, IO = 500mA – 5.0 50.0 mV VI = 8V to 12V – 3.0 50.0 TJ = +25°C VI = 7.3V to 20V – 5.0 50.0 VI = 8V to 12V – 1.5 25.0 Regload Load Regulation(19) TJ = +25°C, IO = 5mA to 1.5A – 9.0 100 mV IO = 5mA to 1A – 9.0 100 IO = 250mA to 750mA – 4.0 50.0 IQ Quiescent Current TJ = +25°C – 5.0 6.0 mA ∆IQ Quiescent Current IO = 5mA to 1A – – 0.5 mA Change VI = 8V to 25V, IO = 500mA – – 0.8 VI = 7.5V to 20V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(20) IO = 5mA – -0.8 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(20) f = 120Hz, IO = 500mA, VI = 8V to 18V – 68.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (20) f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (20) TJ = +25°C – 2.2 – A Notes: 19. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 20. These parameters, although guaranteed, are not 100% tested in production. 12 www.fairchildsemi.com LM78XX/LM78XXA Rev. 1.2 LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7806A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 11V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 5.58 6.0 6.12 V IO = 5mA to 1A, PO ≤ 15W, 5.76 6.0 6.24 VI = 8.6V to 21V Regline Line Regulation(21) VI = 8.6V to 25V, IO = 500mA – 5.0 60.0 mV VI = 9V to 13V – 3.0 60.0 TJ = +25°C VI = 8.3V to 21V – 5.0 60.0 VI = 9V to 13V – 1.5 30.0 Regload Load Regulation(21) TJ = +25°C, IO = 5mA to 1.5A – 9.0 100 mV IO = 5mA to 1A – 9.0 100 IO = 250mA to 750mA – 5.0 50.0 IQ Quiescent Current TJ = +25°C – 4.3 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 19V to 25V, IO = 500mA – – 0.8 VI = 8.5V to 21V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(22) IO = 5mA – -0.8 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(22) f = 120Hz, IO = 500mA, VI = 9V to 19V – 65.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V r Output Resistance(22)O f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (22) TJ = +25°C – 2.2 – A Notes: 21. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 22. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 13 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7808A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 14V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 7.84 8.0 8.16 V IO = 5mA to 1A, PO ≤ 15W, 7.7 8.0 8.3 VI = 10.6V to 23V Regline Line Regulation(23) VI = 10.6V to 25V, IO = 500mA – 6.0 80.0 mV VI = 11V to 17V – 3.0 80.0 TJ = +25°C VI = 10.4V to 23V – 6.0 80.0 VI = 11V to 17V – 2.0 40.0 Regload Load Regulation(23) TJ = +25°C, IO = 5mA to 1.5A – 12.0 100 mV IO = 5mA to 1A – 12.0 100 IO = 250mA to 750mA – 5.0 50.0 IQ Quiescent Current TJ = +25°C – 5.0 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 11V to 25V, IO = 500mA – – 0.8 VI = 10.6V to 23V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(24) IO = 5mA – -0.8 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(24) f = 120Hz, IO = 500mA, – 62.0 – dB VI = 11.5V to 21.5V VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V r Output Resistance(24)O f = 1kHz – 18.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (24) TJ = +25°C – 2.2 – A Notes: 23. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 24. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 14 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7809A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 15V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VO Output Voltage TJ = +25°C 8.82 9.0 9.16 V IO = 5mA to 1A, PO ≤ 15W, 8.65 9.0 9.35 VI = 11.2V to 24V Regline Line Regulation(25) VI = 11.7V to 25V, IO = 500mA – 6.0 90.0 mV VI = 12.5V to 19V – 4.0 45.0 TJ = +25°C VI = 11.5V to 24V – 6.0 90.0 VI = 12.5V to 19V – 2.0 45.0 Regload Load Regulation(25) TJ = +25°C, IO = 5mA to 1.5A – 12.0 100 mV IO = 5mA to 1A – 12.0 100 IO = 250mA to 750mA – 5.0 50.0 IQ Quiescent Current TJ = +25°C – 5.0 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 12V to 25V, IO = 500mA – – 0.8 VI = 11.7V to 25V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(26) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(26) f = 120Hz, IO = 500mA, – 62.0 – dB VI = 12V to 22V VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (26) f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA I (26)PK Peak Current TJ = +25°C – 2.2 – A Notes: 25. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 26. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 15 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7810A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 16V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VO Output Voltage TJ = +25°C 9.8 10.0 10.2 V IO = 5mA to 1A, PO ≤ 15W, 9.6 10.0 10.4 VI = 12.8V to 25V Regline Line Regulation(27) VI = 12.8V to 26V, IO = 500mA – 8.0 100 mV VI = 13V to 20V – 4.0 50.0 TJ = +25°C VI = 12.5V to 25V – 8.0 100 VI = 13V to 20V – 3.0 50.0 Regload Load Regulation(27) TJ = +25°C, IO = 5mA to 1.5A – 12.0 100 mV IO = 5mA to 1A – 12.0 100 IO = 250mA to 750mA – 5.0 50.0 IQ Quiescent Current TJ = +25°C – 5.0 6.0 mA ∆IQ Quiescent Current IO = 5mA to 1A – – 0.5 mA Change VI = 12.8V to 25V, IO = 500mA – – 0.8 VI = 13V to 26V, TJ = +25°C – – 0.5 ∆VO/∆T Output Voltage Drift(28) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(28) f = 120Hz, IO = 500mA, VI = 14V to 24V – 62.0 – dB VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V r Output Resistance(28)O f = 1kHz – 17.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (28) TJ = +25°C – 2.2 – A Notes: 27. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 28. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 16 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7812A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 19V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VO Output Voltage TJ = +25°C 11.75 12.0 12.25 V IO = 5mA to 1A, PO ≤ 15W, 11.5 12.0 12.5 VI = 14.8V to 27V Regline Line Regulation(29) VI = 14.8V to 30V, IO = 500mA – 10.0 120 mV VI = 16V to 22V – 4.0 120 TJ = +25°C VI = 14.5V to 27V – 10.0 120 VI = 16V to 22V – 3.0 60.0 Regload Load Regulation(29) TJ = +25°C, IO = 5mA to 1.5A – 12.0 100 mV IO = 5mA to 1A – 12.0 100 IO = 250mA to 750mA – 5.0 50.0 IQ Quiescent Current TJ = +25°C – 5.1 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 14V to 27V, IO = 500mA – – 0.8 VI = 15V to 30V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(30) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(30) f = 120Hz, IO = 500mA, – 60.0 – dB VI = 14V to 24V VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (30) f = 1kHz – 18.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA I (30)PK Peak Current TJ = +25°C – 2.2 – A Note: 29. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 30. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 17 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7815A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 23V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VO Output Voltage TJ = +25°C 14.75 15.0 15.3 V IO = 5mA to 1A, PO ≤ 15W, 14.4 15.0 15.6 VI = 17.7V to 30V Regline Line Regulation(31) VI = 17.4V to 30V, IO = 500mA – 10.0 150 mV VI = 20V to 26V – 5.0 150 TJ = +25°C VI = 17.5V to 30V – 11.0 150 VI = 20V to 26V – 3.0 75.0 Regload Load Regulation(31) TJ = +25°C, IO = 5mA to 1.5A – 12.0 100 mV IO = 5mA to 1A – 12.0 100 IO = 250mA to 750mA – 5.0 50.0 IQ Quiescent Current TJ = +25°C – 5.2 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 17.5V to 30V, IO = 500mA – – 0.8 VI = 17.5V to 30V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(32) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(32) f = 120Hz, IO = 500mA, – 58.0 – dB VI = 18.5V to 28.5V VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V rO Output Resistance (32) f = 1kHz – 19.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA I (32)PK Peak Current TJ = +25°C – 2.2 – A Notes: 31. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 32. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 18 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7818A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 27V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VO Output Voltage TJ = +25°C 17.64 18.0 18.36 V IO = 5mA to 1A, PO ≤ 15W, 17.3 18.0 18.7 VI = 21V to 33V Regline Line Regulation(33) VI = 21V to 33V, IO = 500mA – 15.0 180 mV VI = 21V to 33V – 5.0 180 TJ = +25°C VI = 20.6V to 33V – 15.0 180 VI = 24V to 30V – 5.0 90.0 Regload Load Regulation(33) TJ = +25°C, IO = 5mA to 1.5A – 15.0 100 mV IO = 5mA to 1A – 15.0 100 IO = 250mA to 750mA – 7.0 50.0 IQ Quiescent Current TJ = +25°C – 5.2 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 12V to 33V, IO = 500mA – – 0.8 VI = 12V to 33V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(34) IO = 5mA – -1.0 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(34) f = 120Hz, IO = 500mA, – 57.0 – dB VI = 22V to 32V VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V r Output Resistance(34)O f = 1kHz – 19.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (34) TJ = +25°C – 2.2 – A Notes: 33. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 34. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 19 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Electrical Characteristics (LM7824A) (Continued) Refer to the test circuits. 0°C < TJ < 125°C, IO = 1A, VI = 33V, CI = 0.33µF, CO = 0.1µF, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VO Output Voltage TJ = +25°C 23.5 24.0 24.5 V IO = 5mA to 1A, PO ≤ 15W, 23.0 24.0 25.0 VI = 27.3V to 38V Regline Line Regulation(35) VI = 27V to 38V, IO = 500mA – 18.0 240 mV VI = 21V to 33V – 6.0 240 TJ = +25°C VI = 26.7V to 38V – 18.0 240 VI = 30V to 36V – 6.0 120 Regload Load Regulation(35) TJ = +25°C, IO = 5mA to 1.5A – 15.0 100 mV IO = 5mA to 1A – 15.0 100 IO = 250mA to 750mA – 7.0 50.0 IQ Quiescent Current TJ = +25°C – 5.2 6.0 mA ∆IQ Quiescent Current Change IO = 5mA to 1A – – 0.5 mA VI = 27.3V to 38V, IO = 500mA – – 0.8 VI = 27.3V to 38V, TJ = +25°C – – 0.8 ∆VO/∆T Output Voltage Drift(36) IO = 5mA – -1.5 – mV/°C VN Output Noise Voltage f = 10Hz to 100kHz, TA = +25°C – 10.0 – µV/VO RR Ripple Rejection(36) f = 120Hz, IO = 500mA, – 54.0 – dB VI = 28V to 38V VDROP Dropout Voltage IO = 1A, TJ = +25°C – 2.0 – V r Output Resistance(36)O f = 1kHz – 20.0 – mΩ ISC Short Circuit Current VI = 35V, TA = +25°C – 250 – mA IPK Peak Current (36) TJ = +25°C – 2.2 – A Notes: 35. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 36. These parameters, although guaranteed, are not 100% tested in production. LM78XX/LM78XXA Rev. 1.2 20 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Typical Performance Characteristics 6 3 VI = 10V TJ = 25°C VO = 5V ∆VO = 100mV IO = 5mA5.75 2.5 5.5 2 5.25 1.5 5 1 4.75 .5 4.5 0 -50 -25 0 25 50 75 100 125 0 5 10 15 20 25 30 35 JUNCTION TEMPERATURE (°C) INPUT-OUTPUT DIFFERENTIAL (V) Figure 3. Quiescent Current Figure 4. Peak Output Current 1.02 7 VI – VO = 5V TJ = 25°C IO = 5mA VO = 5V IO = 10mA6.5 1.01 6 1 5.5 5 0.99 4.5 0.98 4 -50 -25 0 25 50 75 100 125 5 10 15 20 25 30 35 JUNCTION TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 5. Output Voltage Figure 6. Quiescent Current LM78XX/LM78XXA Rev. 1.2 21 www.fairchildsemi.com NORMALIZED OUTPUT VOLTAGE (V) QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) OUTPUT CURRENT (A) LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Typical Applications 1 3 LM78XX Input Output C 2I CO 0.1µF 0.33µF Figure 7. DC Parameters 1 3 LM78XX Input Output 2 RL 270pF VO 2N6121 0V 0.33µF Vor EQ O100Ω 30µS Figure 8. Load Regulation 5.1Ω 1 3 LM78XX Input Output 2 RL 0.33µF 470µF 120Hz + Figure 9. Ripple Rejection LM78XX/LM78XXA Rev. 1.2 22 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator 1 3 LM78XX Input Output C 2I CO 0.1µF 0.33µF Figure 10. Fixed Output Regulator 1 3 LM78XX Output Input C 2I CO 0.1µF VXX 0.33µF R1 IQ IO RL V I XXO = R1 + IQ Notes: 1. To specify an output voltage, substitute voltage value for “XX.” A common ground is required between the input and the output voltage. The input voltage must remain typically 2.0V above the output voltage even during the low point on the input ripple voltage. 2. CI is required if regulator is located an appreciable distance from power supply filter. 3. CO improves stability and transient response. Figure 11. 1 3 Output LM78XX Input C 2 C V 0.1µF XXI O R1 0.33µF IQ R2 IRI ≥ 5 IQ VO = VXX(1 + R2 / R1) + IQR2 Figure 12. Circuit for Increasing Output Voltage LM78XX/LM78XXA Rev. 1.2 23 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Input 1 Output LM7805 3 2 CI 0.33µF - 2 CO 6 LM741 0.1µF + 3 10kΩ 4 IRI ≥ 5 IQ VO = VXX(1 + R2 / R1) + IQR2 Figure 13. Adjustable Output Regulator (7V to 30V) Input Q1 BD536 IQ1 R1 1 3 Output LM78XX 3Ω IREG IO 2 V R1 = BEQ1 0.33µF 0.1µF IREG–IQ1/ BQ1 IO = IREG + BQ1 (IREG–VBEQ1/R1) Figure 14. High Current Voltage Regulator Input R Q1SC Q2 R1 Output1 LM78XX 3 3Ω 2 Q1 = TIP42 0.33µF 0.1µF Q2 = TIP42 V R BEQ2SC = I SC Figure 15. High Output Current with Short Circuit Protection LM78XX/LM78XXA Rev. 1.2 24 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator 1 3 LM78XX VI VO 2 0.33µF 0.1µF 4.7kΩ 7 2 COMMON COMMON _ 6 LM741 + 4 3 4.7kΩ -VIN TIP42 -VO Figure 16. Tracking Voltage Regulator 1 3 LM7815 +20V +15V 0.33µF 2 0.1µF 1N4001 + 2.2µF 1µF + 1 1N4001 2 MC7915 3 -20V -15V Figure 17. Split Power Supply (±15V – 1A) LM78XX/LM78XXA Rev. 1.2 25 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Output Input + 0.1µF 2 1 3 LM78XX Figure 18. Negative Output Voltage Circuit Input D45H11 1mH Output 470Ω 4.7Ω Z1 1 3LM78XX + 20.33µF 10µF 0.5Ω + 2000µF Figure 19. Switching Regulator LM78XX/LM78XXA Rev. 1.2 26 www.fairchildsemi.com LM78XX/LM78XXA 3-Terminal 1A Positive Voltage Regulator Mechanical Dimensions Dimensions in millimeters TO-220 [ SINGLE GAUGE ] © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX/LM78XXA Rev. 1.2 27 LM78XX/LM78XXA — 3-Terminal 1A Positive Voltage Regulator TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 2Cool F-PFS PowerTrench® The Power Franchise® AccuPower FRFET® PowerXS™ AX-CAP * Global Power Resource SM Programmable Active Droop ® BitSiC GreenBridge QFET Green FPS QS TinyBoostBuild it Now CorePLUS Green FPS e-Series Quiet Series TinyBuck TinyCalc CorePOWER Gmax RapidConfigure TinyLogic® CROSSVOLT GTO TINYOPTO CTL IntelliMAX Saving our world, 1mW/W/kW at a time™ TinyPower Current Transfer Logic ISOPLANAR SignalWise DEUXPEED® Making Small Speakers Sound Louder TinyPWM SmartMax TinyWire Dual Cool™ and Better™ SMART START EcoSPARK® MegaBuck TranSiC EfficientMax MICROCOUPLER Solutions for Your Success TriFault Detect MicroFET SPM ® TRUECURRENT®* ESBC ® MicroPak STEALTH SerDesSuperFET® ® MicroPak2Fairchild SuperSOT -3 MillerDrive Fairchild Semiconductor® SuperSOT -6 ®MotionMax UHC FACT Quiet Series SuperSOT -8 Motion-SPM Ultra FRFET FACT® SupreMOS ® FAST® mWSaver UniFET SyncFET VCX FastvCore OptoHiT ® Sync-Lock™ OPTOLOGIC VisualMax FETBench OPTOPLANAR® ®* VoltagePlusFlashWriter®* XS™ FPS ® * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I61 © Fairchild Semiconductor Corporation www.fairchildsemi.com LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 LM117/LM317A/LM317-N 3-Terminal Adjustable Regulator Check for Samples: LM117, LM317-N FEATURES Normally, no capacitors are needed unless the device1 is situated more than 6 inches from the input filter 2• Specified 1% Output Voltage Tolerance capacitors in which case an input bypass is needed. (LM317A) An optional output capacitor can be added to improve • Specified Max. 0.01%/V Line Regulation transient response. The adjustment terminal can be (LM317A) bypassed to achieve very high ripple rejection ratios • Specified Max. 0.3% Load Regulation (LM117) which are difficult to achieve with standard 3-terminal regulators. • Specified 1.5A Output Current • Adjustable Output Down to 1.2V Besides replacing fixed regulators, the LM117 is useful in a wide variety of other applications. Since • Current Limit Constant With Temperature the regulator is “floating” and sees only the input-to- • P+ Product Enhancement Tested output differential voltage, supplies of several • 80 dB Ripple Rejection hundred volts can be regulated as long as the maximum input to output differential is not exceeded, • Output is Short-Circuit Protected i.e., avoid short-circuiting the output. DESCRIPTION Also, it makes an especially simple adjustable switching regulator, a programmable output regulator, The LM117 series of adjustable 3-terminal positive or by connecting a fixed resistor between the voltage regulators is capable of supplying in excess adjustment pin and output, the LM117 can be used of 1.5A over a 1.2V to 37V output range. They are as a precision current regulator. Supplies with exceptionally easy to use and require only two electronic shutdown can be achieved by clamping the external resistors to set the output voltage. Further, adjustment terminal to ground which programs the both line and load regulation are better than standard output to 1.2V where most loads draw little current. fixed regulators. Also, the LM117 is packaged in standard transistor packages which are easily For applications requiring greater output current, see mounted and handled. LM150 series (3A) and LM138 series (5A) data sheets. For the negative complement, see LM137 In addition to higher performance than fixed series data sheet. regulators, the LM117 series offers full overload protection available only in IC's. Included on the chip are current limit, thermal overload protection and safe area protection. All overload protection circuitry remains fully functional even if the adjustment terminal is disconnected. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2004–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Typical Applications Figure 1. 1.2V–25V Adjustable Regulator LM117/LM317A/LM317-N Package Options Part Number Suffix Package OutputCurrent LM117, LM317-N NDS TO-3 1.5A LM317A, LM317-N NDE TO-220 1.5A LM317-N KTT TO-263 1.5A LM317A, LM317-N DCY SOT-223 1.0A LM117, LM317A, LM317-N NDT TO 0.5A LM117 NAJ LCCC 0.5A LM317A, LM317-N NDP PFM 0.5A Full output current not available at high SOT-223 vs. PFM Packages input-output voltages *Needed if device is more than 6 inches from filter capacitors. †Optional—improves transient response. Output capacitors in the range of 1μF to 1000μF of aluminum or tantalum electrolytic are commonly used to provide improved output impedance and rejection of transients. Figure 2. Scale 1:1 Connection Diagrams TO-3 (NDS) Metal Can Package Figure 5. TO-263 (KTT) Surface-Mount Package Figure 6. Top View CASE IS OUTPUT Figure 3. Bottom View TO-263 (KTT) Bottom View Surface-Mount Package Package Number NDS or K TO (NDT) Figure 7. Side View Metal Can Package Package Number KTT CASE IS OUTPUT Figure 4. Bottom View Package Number NDT 2 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 TO-220 (NDE) 4-Lead SOT-223 (DCY) Plastic Package Figure 10. Front View Package Number DCY PFM (NDP) Figure 8. Front View Package Number NDE Ceramic Leadless Chip Carrier (NAJ) Figure 11. Front View Package Number NDP Figure 9. Top View Package Number NAJ Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Power Dissipation Internally Limited Input-Output Voltage Differential +40V, −0.3V Storage Temperature −65°C to +150°C Lead Temperature Metal Package (Soldering, 10 seconds) 300°C Plastic Package (Soldering, 4 seconds) 260°C ESD Tolerance (3) 3 kV (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) Human body model, 100 pF discharged through a 1.5 kΩ resistor. Operating Temperature Range LM117 −55°C ≤ TJ ≤ +150°C LM317A −40°C ≤ TJ ≤ +125°C LM317-N 0°C ≤ TJ ≤ +125°C Preconditioning Thermal Limit Burn-In All Devices 100% LM117 Electrical Characteristics (1) Specifications with standard type face are for TJ = 25°C, and those with boldface type apply over full Operating Temperature Range. Unless otherwise specified, VIN − VOUT = 5V, and IOUT = 10 mA. LM117 (2) Parameter Conditions Min Typ Max Units Reference Voltage 3V ≤ (VIN − VOUT) ≤ 40V,10 mA ≤ I ≤ I (1) 1.20 1.25 1.30 VOUT MAX Line Regulation 3V ≤ (VIN − VOUT) ≤ 40V (3) 0.01 0.02 0.02 0.05 %/V Load Regulation 10 mA ≤ I ≤ I (1) (3) 0.1 0.3OUT MAX 0.3 1 % Thermal Regulation 20 ms Pulse 0.03 0.07 %/W Adjustment Pin Current 50 100 μA Adjustment Pin Current Change 10 mA ≤ I (1) OUT ≤ IMAX 3V ≤ (VIN − VOUT) ≤ 40V 0.2 5 μA Temperature Stability TMIN ≤ TJ ≤ TMAX 1 % Minimum Load Current (VIN − VOUT) = 40V 3.5 5 mA NDS Package 1.5 2.2 3.4 (VIN − VOUT) ≤ 15V A NDT, NAJ Package 0.5 0.8 1.8 Current Limit NDS Package 0.3 0.4 (VIN − VOUT) = 40V A NDT, NAJ Package 0.15 0.20 RMS Output Noise, % of VOUT 10 Hz ≤ f ≤ 10 kHz 0.003 % (1) IMAX = 1.5A for the NDS (TO-3), NDE (TO-220), and KTT (TO-263) packages. IMAX = 1.0A for the DCY (SOT-223) package. IMAX = 0.5A for the NDT (TO), MDT (PFM), and NAJ (LCCC) packages. Device power dissipation (PD) is limited by ambient temperature (TA), device maximum junction temperature (TJ), and package thermal resistance (θJA). The maximum allowable power dissipation at any temperature is : PD(MAX) = ((TJ(MAX) - TA)/θJA). All Min. and Max. limits are ensured to TI's Average Outgoing Quality Level (AOQL). (2) Refer to RETS117H drawing for the LM117H, or the RETS117K for the LM117K military specifications. (3) Regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specifications for thermal regulation. 4 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 LM117 Electrical Characteristics(1) (continued) Specifications with standard type face are for TJ = 25°C, and those with boldface type apply over full Operating Temperature Range. Unless otherwise specified, VIN − VOUT = 5V, and IOUT = 10 mA. LM117 (2) Parameter Conditions Min Typ Max Units VOUT = 10V, f = 120 Hz, CADJ = 0 μF 65 dB Ripple Rejection Ratio VOUT = 10V, f = 120 Hz, CADJ = 10 μF 66 80 dB Long-Term Stability TJ = 125°C, 1000 hrs 0.3 1 % NDS (TO-3) Package 2 Thermal Resistance, θJC Junction-to-Case NDT (TO) Package 21 °C/W NAJ (LCCC) Package 12 Thermal Resistance, θ NDS (TO-3) Package 39JA Junction-to-Ambient NDT (TO) Package 186 °C/W (No Heat Sink) NAJ (LCCC) Package 88 LM317A and LM317-N Electrical Characteristics (1) Specifications with standard type face are for TJ = 25°C, and those with boldface type apply over full Operating Temperature Range. Unless otherwise specified, VIN − VOUT = 5V, and IOUT = 10 mA. LM317A LM317-N Parameter Conditions Min Typ Max Min Typ Max Units 1.238 1.250 1.262 - 1.25 - V Reference Voltage 3V ≤ (VIN − VOUT) ≤ 40V, 10 mA ≤ I ≤ I (1) 1.225 1.250 1.270 1.20 1.25 1.30 VOUT MAX Line Regulation 3V ≤ (V − V ) ≤ 40V (2) 0.005 0.01 0.01 0.04IN OUT 0.01 0.02 0.02 0.07 %/V Load Regulation 10 mA ≤ IOUT ≤ I (1) (2) 0.1 0.5 0.1 0.5 MAX 0.3 1 0.3 1.5 % Thermal Regulation 20 ms Pulse 0.04 0.07 0.04 0.07 %/W Adjustment Pin Current 50 100 50 100 μA Adjustment Pin Current 10 mA ≤ I ≤ I (1)OUT MAX Change 3V ≤ (V − V ) ≤ 40V 0.2 5 0.2 5 μAIN OUT Temperature Stability TMIN ≤ TJ ≤ TMAX 1 1 % Minimum Load Current (VIN − VOUT) = 40V 3.5 10 3.5 10 mA NDS, KTT Packages - - - 1.5 2.2 3.4 (VIN − VOUT) ≤ 15V DCY, NDE Packages 1.5 2.2 3.4 1.5 2.2 3.4 A NDT, MDT Packages 0.5 0.8 1.8 0.5 0.8 1.8 Current Limit NDS, KTT Packages - - 0.15 0.40 (VIN − VOUT) = 40V DCY, NDE Packages 0.112 0.30 0.112 0.30 A NDT, MDT Packages 0.075 0.20 0.075 0.20 RMS Output Noise, % of V 10 Hz ≤ f ≤ 10 kHz 0.003 0.003 %OUT VOUT = 10V, f = 120 Hz, CADJ = 0 μF 65 65 dB Ripple Rejection Ratio VOUT = 10V, f = 120 Hz, CADJ = 10 μF 66 80 66 80 dB Long-Term Stability TJ = 125°C, 1000 hrs 0.3 1 0.3 1 % (1) IMAX = 1.5A for the NDS (TO-3), NDE (TO-220), and KTT (TO-263) packages. IMAX = 1.0A for the DCY (SOT-223) package. IMAX = 0.5A for the NDT (TO), MDT (PFM), and NAJ (LCCC) packages. Device power dissipation (PD) is limited by ambient temperature (TA), device maximum junction temperature (TJ), and package thermal resistance (θJA). The maximum allowable power dissipation at any temperature is : PD(MAX) = ((TJ(MAX) - TA)/θJA). All Min. and Max. limits are ensured to TI's Average Outgoing Quality Level (AOQL). (2) Regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specifications for thermal regulation. Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com LM317A and LM317-N Electrical Characteristics(1) (continued) Specifications with standard type face are for TJ = 25°C, and those with boldface type apply over full Operating Temperature Range. Unless otherwise specified, VIN − VOUT = 5V, and IOUT = 10 mA. LM317A LM317-N Parameter Conditions Min Typ Max Min Typ Max Units NDS (TO-3) Package - 2 NDE (TO-220) Package 4 4 Thermal Resistance, θ KTT (TO-263) Package - 4JC Junction-to-Case °C/WDCY (SOT-223) Package 23.5 23.5 NDT (TO) Package 21 21 MDT (PFM) Package 12 12 NDS (TO-3) Package - 39 NDE (TO-220) Package 50 50 Thermal Resistance, θJA KTT (TO-263) Package (3) - 50 Junction-to-Ambient (No (3) °C/W Heat Sink) DCY (SOT-223) Package 140 140 NDT (TO) Package 186 186 MDT (PFM) Package (3) 103 103 (3) When surface mount packages are used (TO-263, SOT-223, PFM), the junction to ambient thermal resistance can be reduced by increasing the PC board copper area that is thermally connected to the package. See the Applications Hints section for heatsink techniques. 6 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 Typical Performance Characteristics Output Capacitor = 0 μF unless otherwise noted Load Regulation Current Limit Figure 12. Figure 13. Adjustment Current Dropout Voltage Figure 14. Figure 15. VOUT vs VIN, VOUT = VREF VOUT vs VIN, VOUT = 5V Figure 16. Figure 17. Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Typical Performance Characteristics (continued) Output Capacitor = 0 μF unless otherwise noted Temperature Stability Minimum Operating Current Figure 18. Figure 19. Ripple Rejection Ripple Rejection Figure 20. Figure 21. Ripple Rejection Output Impedance Figure 22. Figure 23. 8 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 Typical Performance Characteristics (continued) Output Capacitor = 0 μF unless otherwise noted Line Transient Response Load Transient Response Figure 24. Figure 25. APPLICATION HINTS In operation, the LM117 develops a nominal 1.25V reference voltage, VREF, between the output and adjustment terminal. The reference voltage is impressed across program resistor R1 and, since the voltage is constant, a constant current I1 then flows through the output set resistor R2, giving an output voltage of (1) Since the 100μA current from the adjustment terminal represents an error term, the LM117 was designed to minimize IADJ and make it very constant with line and load changes. To do this, all quiescent operating current is returned to the output establishing a minimum load current requirement. If there is insufficient load on the output, the output will rise. External Capacitors An input bypass capacitor is recommended. A 0.1μF disc or 1μF solid tantalum on the input is suitable input bypassing for almost all applications. The device is more sensitive to the absence of input bypassing when adjustment or output capacitors are used but the above values will eliminate the possibility of problems. The adjustment terminal can be bypassed to ground on the LM117 to improve ripple rejection. This bypass capacitor prevents ripple from being amplified as the output voltage is increased. With a 10 μF bypass capacitor 80dB ripple rejection is obtainable at any output level. Increases over 10 μF do not appreciably improve the ripple rejection at frequencies above 120Hz. If the bypass capacitor is used, it is sometimes necessary to include protection diodes to prevent the capacitor from discharging through internal low current paths and damaging the device. Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com In general, the best type of capacitors to use is solid tantalum. Solid tantalum capacitors have low impedance even at high frequencies. Depending upon capacitor construction, it takes about 25 μF in aluminum electrolytic to equal 1μF solid tantalum at high frequencies. Ceramic capacitors are also good at high frequencies; but some types have a large decrease in capacitance at frequencies around 0.5 MHz. For this reason, 0.01 μF disc may seem to work better than a 0.1 μF disc as a bypass. Although the LM117 is stable with no output capacitors, like any feedback circuit, certain values of external capacitance can cause excessive ringing. This occurs with values between 500 pF and 5000 pF. A 1 μF solid tantalum (or 25 μF aluminum electrolytic) on the output swamps this effect and insures stability. Any increase of the load capacitance larger than 10 μF will merely improve the loop stability and output impedance. Load Regulation The LM117 is capable of providing extremely good load regulation but a few precautions are needed to obtain maximum performance. The current set resistor connected between the adjustment terminal and the output terminal (usually 240Ω) should be tied directly to the output (case) of the regulator rather than near the load. This eliminates line drops from appearing effectively in series with the reference and degrading regulation. For example, a 15V regulator with 0.05Ω resistance between the regulator and load will have a load regulation due to line resistance of 0.05Ω × IL. If the set resistor is connected near the load the effective line resistance will be 0.05Ω (1 + R2/R1) or in this case, 11.5 times worse. Figure 26 shows the effect of resistance between the regulator and 240Ω set resistor. Figure 26. Regulator with Line Resistance in Output Lead With the TO-3 package, it is easy to minimize the resistance from the case to the set resistor, by using two separate leads to the case. However, with the TO package, care should be taken to minimize the wire length of the output lead. The ground of R2 can be returned near the ground of the load to provide remote ground sensing and improve load regulation. Protection Diodes When external capacitors are used with any IC regulator it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Most 10 μF capacitors have low enough internal series resistance to deliver 20A spikes when shorted. Although the surge is short, there is enough energy to damage parts of the IC. When an output capacitor is connected to a regulator and the input is shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage of the regulator, and the rate of decrease of VIN. In the LM117, this discharge path is through a large junction that is able to sustain 15A surge with no problem. This is not true of other types of positive regulators. For output capacitors of 25 μF or less, there is no need to use diodes. The bypass capacitor on the adjustment terminal can discharge through a low current junction. Discharge occurs when either the input, or the output, is shorted. Internal to the LM117 is a 50Ω resistor which limits the peak discharge current. No protection is needed for output voltages of 25V or less and 10 μF capacitance. Figure 27 shows an LM117 with protection diodes included for use with outputs greater than 25V and high values of output capacitance. 10 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 D1 protects against C1 D2 protects against C2 Figure 27. Regulator with Protection Diodes Heatsink Requirements The LM317-N regulators have internal thermal shutdown to protect the device from over-heating. Under all operating conditions, the junction temperature of the LM317-N should not exceed the rated maximum junction temperature (TJ) of 150°C for the LM117, or 125°C for the LM317A and LM317-N. A heatsink may be required depending on the maximum device power dissipation and the maximum ambient temperature of the application. To determine if a heatsink is needed, the power dissipated by the regulator, PD, must be calculated: PD = ((VIN − VOUT) × IL) + (VIN × IG) (2) Figure 28 shows the voltage and currents which are present in the circuit. The next parameter which must be calculated is the maximum allowable temperature rise, TR(MAX): TR(MAX) = TJ(MAX) − TA(MAX) (3) where TJ(MAX) is the maximum allowable junction temperature (150°C for the LM117, or 125°C for the LM317A/LM317-N), and TA(MAX) is the maximum ambient temperature which will be encountered in the application. Using the calculated values for TR(MAX) and PD, the maximum allowable value for the junction-to-ambient thermal resistance (θJA) can be calculated: θJA = (TR(MAX) / PD) (4) Figure 28. Power Dissipation Diagram If the calculated maximum allowable thermal resistance is higher than the actual package rating, then no additional work is needed. If the calculated maximum allowable thermal resistance is lower than the actual package rating either the power dissipation (PD) needs to be reduced, the maximum ambient temperature TA(MAX) needs to be reduced, the thermal resistance (θJA) must be lowered by adding a heatsink, or some combination of these. If a heatsink is needed, the value can be calculated from the formula: θHA ≤ (θJA - (θCH + θJC)) (5) Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com where (θCH is the thermal resistance of the contact area between the device case and the heatsink surface, and θJC is thermal resistance from the junction of the die to surface of the package case. When a value for θ(H−A) is found using the equation shown, a heatsink must be selected that has a value that is less than, or equal to, this number. The θ(H−A) rating is specified numerically by the heatsink manufacturer in the catalog, or shown in a curve that plots temperature rise vs power dissipation for the heatsink. Heatsinking Surface Mount Packages The TO-263 (KTT), SOT-223 (DCY) and PFM (MDT) packages use a copper plane on the PCB and the PCB itself as a heatsink. To optimize the heat sinking ability of the plane and PCB, solder the tab of the package to the plane. Heatsinking the SOT-223 Package Figure 29 and Figure 30 show the information for the SOT-223 package. Figure 30 assumes a θ(J−A) of 74°C/W for 1 ounce copper and 51°C/W for 2 ounce copper and a maximum junction temperature of 125°C. Please see AN-1028 (literature number SNVA036) for thermal enhancement techniques to be used with SOT-223 and PFM packages. Figure 29. θ(J−A) vs Copper (2 ounce) Area for the SOT-223 Package Figure 30. Maximum Power Dissipation vs TAMB for the SOT-223 Package Heatsinking the TO-263 Package Figure 31 shows for the TO-263 the measured values of θ(J−A) for different copper area sizes using a typical PCB with 1 ounce copper and no solder mask over the copper area used for heatsinking. 12 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 As shown in Figure 31, increasing the copper area beyond 1 square inch produces very little improvement. It should also be observed that the minimum value of θ(J−A) for the TO-263 package mounted to a PCB is 32°C/W. Figure 31. θ(J−A) vs Copper (1 ounce) Area for the TO-263 Package As a design aid, Figure 32 shows the maximum allowable power dissipation compared to ambient temperature for the TO-263 device (assuming θ(J−A) is 35°C/W and the maximum junction temperature is 125°C). Figure 32. Maximum Power Dissipation vs TAMB for the TO-263 Package Heatsinking the PFM Package If the maximum allowable value for θJA is found to be ≥103°C/W (Typical Rated Value) for PFM package, no heatsink is needed since the package alone will dissipate enough heat to satisfy these requirements. If the calculated value for θJA falls below these limits, a heatsink is required. As a design aid, Table 1 shows the value of the θJA of PFM for different heatsink area. The copper patterns that we used to measure these θJAs are shown in Figure 37. Figure 33 reflects the same test results as what are in Table 1. Figure 34 shows the maximum allowable power dissipation vs. ambient temperature for the PFM device. Figure 35 shows the maximum allowable power dissipation vs. copper area (in2) for the PFM device. Please see AN-1028 (literature number SNVA036) for thermal enhancement techniques to be used with SOT-223 and PFM packages. Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Table 1. θJA Different Heatsink Area Layout Copper Area Thermal Resistance Top Side (in2) (1) Bottom Side (in2) (θJA°C/W) PFM 1 0.0123 0 103 2 0.066 0 87 3 0.3 0 60 4 0.53 0 54 5 0.76 0 52 6 1.0 0 47 7 0.066 0.2 84 8 0.066 0.4 70 9 0.066 0.6 63 10 0.066 0.8 57 11 0.066 1.0 57 12 0.066 0.066 89 13 0.175 0.175 72 14 0.284 0.284 61 15 0.392 0.392 55 16 0.5 0.5 53 (1) Tab of device attached to topside of copper. Figure 33. θJA vs 2oz Copper Area for PFM Figure 34. Maximum Allowable Power Dissipation vs. Ambient Temperature for PFM 14 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 Figure 35. Maximum Allowable Power Dissipation vs. 2oz Copper Area for PFM Figure 36. Top View of the Thermal Test Pattern in Actual Scale Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Figure 37. Bottom View of the Thermal Test Pattern in Actual Scale Schematic Diagram 16 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 Typical Applications Note: Min. output ≊ 1.2V Figure 38. 5V Logic Regulator with Electronic Shutdown Figure 39. Slow Turn-On 15V Regulator Figure 40. †Solid tantalum *Discharges C1 if output is shorted to ground Figure 41. Adjustable Regulator with Improved Ripple Rejection Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Figure 42. High Stability 10V Regulator ‡Optional—improves ripple rejection †Solid tantalum *Minimum load current = 30 mA Figure 43. High Current Adjustable Regulator 18 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Full output current not available at high input-output voltages Figure 44. 0 to 30V Regulator Figure 45. Power Follower Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com †Solid tantalum *Lights in constant current mode Figure 46. 5A Constant Voltage/Constant Current Regulator Figure 47. 1A Current Regulator *Minimum load current ≊ 4 mA Figure 48. 1.2V–20V Regulator with Minimum Program Current 20 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 Figure 49. High Gain Amplifier †Solid tantalum *Core—Arnold A-254168-2 60 turns Figure 50. Low Cost 3A Switching Regulator Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com †Solid tantalum *Core—Arnold A-254168-2 60 turns Figure 51. 4A Switching Regulator with Overload Protection Figure 52. Precision Current Limiter Figure 53. Tracking Preregulator 22 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 (Compared to LM117's higher current limit) —At 50 mA output only ¾ volt of drop occurs in R3 and R4 Figure 54. Current Limited Voltage Regulator Note: All outputs within ±100 mV †Minimum load—10 mA Figure 55. Adjusting Multiple On-Card Regulators with Single Control Figure 56. AC Voltage Regulator Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: LM117 LM317-N LM117, LM317-N SNVS774L –MAY 2004–REVISED FEBRUARY 2011 www.ti.com Use of RS allows low charging rates with fully charged battery. Figure 57. 12V Battery Charger Figure 58. Figure 59. 50mA Constant Current Battery Charger Figure 60. Adjustable 4A Regulator 24 Submit Documentation Feedback Copyright © 2004–2011, Texas Instruments Incorporated Product Folder Links: LM117 LM317-N LM117, LM317-N www.ti.com SNVS774L –MAY 2004–REVISED FEBRUARY 2011 *Sets peak current (0.6A for 1Ω) **The 1000μF is recommended to filter out input transients Figure 61. Current Limited 6V Charger *Sets maximum VOUT Figure 62. Digitally Selected Outputs Copyright © 2004–2011, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: LM117 LM317-N PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing Qty (2) (3) (4) LM117H ACTIVE TO NDT 3 500 Green (RoHS POST-PLATE Level-1-NA-UNLIM -55 to 125 LM117HP+ & no Sb/Br) LM117H/NOPB ACTIVE TO NDT 3 500 Green (RoHS POST-PLATE Level-1-NA-UNLIM -55 to 125 LM117HP+ & no Sb/Br) LM117K ACTIVE TO-3 NDS 2 50 TBD Call TI Call TI -55 to 125 LM117K STEELP+ LM117K STEEL ACTIVE TO-3 NDS 2 50 TBD Call TI Call TI -55 to 125 LM117K STEELP+ LM117K STEEL/NOPB ACTIVE TO-3 NDS 2 50 Green (RoHS POST-PLATE Level-1-NA-UNLIM -55 to 125 LM117K & no Sb/Br) STEELP+ LM317AEMP ACTIVE SOT-223 DCY 4 1000 TBD Call TI Call TI -40 to 125 N07A LM317AEMP/NOPB ACTIVE SOT-223 DCY 4 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 N07A & no Sb/Br) LM317AEMPX ACTIVE SOT-223 DCY 4 2000 TBD Call TI Call TI N07A LM317AEMPX/NOPB ACTIVE SOT-223 DCY 4 2000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 N07A & no Sb/Br) LM317AH ACTIVE TO NDT 3 500 Green (RoHS POST-PLATE Level-1-NA-UNLIM -40 to 125 LM317AHP+ & no Sb/Br) LM317AH/NOPB ACTIVE TO NDT 3 500 Green (RoHS POST-PLATE Level-1-NA-UNLIM -40 to 125 LM317AHP+ & no Sb/Br) LM317AMDT ACTIVE PFM NDP 3 75 TBD Call TI Call TI -40 to 125 LM317 AMDT LM317AMDT/NOPB ACTIVE PFM NDP 3 75 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 LM317 & no Sb/Br) AMDT LM317AMDTX ACTIVE PFM NDP 3 2500 TBD Call TI Call TI -40 to 125 LM317 AMDT LM317AMDTX/NOPB ACTIVE PFM NDP 3 2500 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 125 LM317 & no Sb/Br) AMDT LM317AT ACTIVE TO-220 NDE 3 45 TBD Call TI Call TI -40 to 125 LM317AT P+ LM317AT/NOPB ACTIVE TO-220 NDE 3 45 Pb-Free (RoHS CU SN Level-1-NA-UNLIM -40 to 125 LM317AT P+ Exempt) LM317EMP ACTIVE SOT-223 DCY 4 1000 TBD Call TI Call TI 0 to 125 N01A Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing Qty (2) (3) (4) LM317EMP/NOPB ACTIVE SOT-223 DCY 4 1000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 125 N01A & no Sb/Br) LM317EMPX/NOPB ACTIVE SOT-223 DCY 4 2000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 125 N01A & no Sb/Br) LM317H ACTIVE TO NDT 3 500 Green (RoHS POST-PLATE Level-1-NA-UNLIM 0 to 125 LM317HP+ & no Sb/Br) LM317H/NOPB ACTIVE TO NDT 3 500 Green (RoHS POST-PLATE Level-1-NA-UNLIM 0 to 125 LM317HP+ & no Sb/Br) LM317K STEEL ACTIVE TO-3 NDS 2 50 TBD Call TI Call TI 0 to 125 LM317K STEELP+ LM317K STEEL/NOPB ACTIVE TO-3 NDS 2 50 Green (RoHS POST-PLATE Level-1-NA-UNLIM 0 to 125 LM317K & no Sb/Br) STEELP+ LM317MDT/NOPB ACTIVE PFM NDP 3 75 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 125 LM317 & no Sb/Br) MDT LM317MDTX/NOPB ACTIVE PFM NDP 3 2500 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 125 LM317 & no Sb/Br) MDT LM317S/NOPB ACTIVE DDPAK/ KTT 3 45 Pb-Free (RoHS CU SN Level-3-245C-168 HR 0 to 125 LM317S TO-263 Exempt) P+ LM317SX/NOPB ACTIVE DDPAK/ KTT 3 500 Pb-Free (RoHS CU SN Level-3-245C-168 HR 0 to 125 LM317S TO-263 Exempt) P+ LM317T ACTIVE TO-220 NDE 3 45 TBD Call TI Call TI LM317T P+ LM317T/LF01 ACTIVE TO-220 NDG 3 45 Pb-Free (RoHS CU SN Level-4-260C-72 HR LM317T P+ Exempt) LM317T/NOPB ACTIVE TO-220 NDE 3 45 Green (RoHS CU SN Level-1-NA-UNLIM 0 to 125 LM317T P+ & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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Addendum-Page 3 www.ti.com PACKAGE MATERIALS INFORMATION 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) LM317AEMP SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317AEMP/NOPB SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317AEMPX SOT-223 DCY 4 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317AEMPX/NOPB SOT-223 DCY 4 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317AMDTX PFM NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LM317AMDTX/NOPB PFM NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LM317EMP SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317EMP/NOPB SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317EMPX/NOPB SOT-223 DCY 4 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM317MDTX/NOPB PFM NDP 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 LM317SX/NOPB DDPAK/ KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM317AEMP SOT-223 DCY 4 1000 367.0 367.0 35.0 LM317AEMP/NOPB SOT-223 DCY 4 1000 367.0 367.0 35.0 LM317AEMPX SOT-223 DCY 4 2000 367.0 367.0 35.0 LM317AEMPX/NOPB SOT-223 DCY 4 2000 367.0 367.0 35.0 LM317AMDTX PFM NDP 3 2500 367.0 367.0 35.0 LM317AMDTX/NOPB PFM NDP 3 2500 367.0 367.0 38.0 LM317EMP SOT-223 DCY 4 1000 367.0 367.0 35.0 LM317EMP/NOPB SOT-223 DCY 4 1000 367.0 367.0 35.0 LM317EMPX/NOPB SOT-223 DCY 4 2000 367.0 367.0 35.0 LM317MDTX/NOPB PFM NDP 3 2500 367.0 367.0 38.0 LM317SX/NOPB DDPAK/TO-263 KTT 3 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDT0003A H03A (Rev D) www.ti.com MECHANICAL DATA NDS0002A www.ti.com MECHANICAL DATA NDE0003B www.ti.com MECHANICAL DATA NDG0003F T03F (Rev B) www.ti.com MECHANICAL DATA NDP0003B TD03B (Rev F) www.ti.com MECHANICAL DATA MPDS094A – APRIL 2001 – REVISED JUNE 2002 DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE 6,70 (0.264) 6,30 (0.248) 3,10 (0.122) 2,90 (0.114) 4 0,10 (0.004) M 7,30 (0.287) 3,70 (0.146) 6,70 (0.264) 3,30 (0.130) Gauge Plane 1 2 3 0,84 (0.033) 0,25 (0.010) 2,30 (0.091) 0°–10° 0,66 (0.026) 0,10 (0.004) 4,60 (0.181) M 0,75 (0.030) MIN 1,70 (0.067) 1,80 (0.071) MAX 1,50 (0.059) 0,35 (0.014) 0,23 (0.009) Seating Plane 0,10 (0.0040) 0,08 (0.003) 0,02 (0.0008) 4202506/B 06/2002 NOTES: A. All linear dimensions are in millimeters (inches). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC TO-261 Variation AA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 KTT0003B MECHANICAL DATA TS3B (Rev F) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated www.fairchildsemi.com LM2902,LM324/LM324A,LM224/ LM224A Quad Operational Amplifier Features Description • Internally Frequency Compensated for Unity Gain The LM324/LM324A,LM2902,LM224/LM224A consist of • Large DC Voltage Gain: 100dB four independent, high gain, internally frequency • Wide Power Supply Range: compensated operational amplifiers which were designed LM224/LM224A, LM324/LM324A : 3V~32V (or ±1.5 ~ specifically to operate from a single power supply over a 16V) wide voltage range. operation from split power supplies is LM2902: 3V~26V (or ±1.5V ~ 13V) also possible so long as the difference between the two • Input Common Mode Voltage Range Includes Ground supplies is 3 volts to 32 volts. Application areas include • Large Output Voltage Swing: 0V to VCC -1.5V transducer amplifier, DC gain blocks and all the • Power Drain Suitable for Battery Operation conventional OP Amp circuits which now can be easily implemented in single power supply systems. 14-DIP 1 14-SOP 1 Internal Block Diagram OUT1 1 14 OUT4 IN1 (-) 2 1 4 13 IN4 (-) _ _ + + IN1 (+) 3 12 IN4 (+) VCC 4 11 GND IN2 (+) 5 _ + + _ 10 IN3 (+) IN2 (-) 6 2 3 9 IN3 (-) OUT2 7 8 OUT3 Rev. 1.0.4 ©2002 Fairchild Semiconductor Corporation LM2902,LM324/LM324A,LM224/LM224A Schematic Diagram (One Section Only) VCC Q5 Q6 Q12 Q17 Q19 Q20 Q2 Q3 R1 C1 IN(-) Q4 Q18 Q1 R2 IN(+) Q11 OUTPUT Q21 Q10 Q15 Q7 Q8 Q9 Q14Q13 Q16 GND Absolute Maximum Ratings Parameter Symbol LM224/LM224A LM324/LM324A LM2902 Unit Power Supply Voltage VCC ±16 or 32 ±16 or 32 ±13 or 26 V Differential Input Voltage VI(DIFF) 32 32 26 V Input Voltage VI -0.3 to +32 -0.3 to +32 -0.3 to +26 V Output Short Circuit to GND ≤ ° - Continuous Continuous Continuous -Vcc 15V, TA=25 C(one Amp) Power Dissipation, TA=25°C 14-DIP PD 1310 1310 1310 mW 14-SOP 640 640 640 Operating Temperature Range TOPR -25 ~ +85 0 ~ +70 -40 ~ +85 °C Storage Temperature Range TSTG -65 ~ +150 -65 ~ +150 -65 ~ +150 °C Thermal Data Parameter Symbol Value Unit Thermal Resistance Junction-Ambient Max. 14-DIP Rθja 95 °C/W 14-SOP 195 2 LM2902,LM324/LM324A,LM224/LM224A Electrical Characteristics (VCC = 5.0V, VEE = GND, TA = 25°C, unless otherwise specified) LM224 LM324 LM2902 Parameter Symbol Conditions Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. VCM = 0V to VCC Input Offset -1.5V VIO - 1.5 5.0 - 1.5 7.0 - 1.5 7.0 mV Voltage VO(P) = 1.4V, RS = 0Ω (Note1) Input Offset IIO VCM = 0V - 2.0 30 - 3.0 50 - 3.0 50 nA Current Input Bias Current IBIAS VCM = 0V - 40 150 - 40 250 - 40 250 nA Input Common- VCC VCC VCC Mode Voltage VI(R) Note1 0 - 0 -1.5 - 0 - -1.5 V -1.5 Range RL = ∞,VCC = 30V - 1.0 3 - 1.0 3 - 1.0 3 mA Supply Current ICC (LM2902,VCC=26V) RL = ∞,VCC = 5V - 0.7 1.2 - 0.7 1.2 - 0.7 1.2 mA Large Signal VCC = 15V,RL=2kΩ V/ GV 50 100 - 25 100 - 25 100 - Voltage Gain VO(P) = 1V to 11V mV RL = 2kΩ 26 - - 26 - - 22 - - V Output Voltage VO(H) Note1 RL=10kΩ 27 28 - 27 28 - 23 24 - V Swing VO(L) VCC = 5V,RL=10kΩ - 5 20 - 5 20 - 5 100 mV Common-Mode CMRR - 70 85 - 65 75 - 50 75 - dB Rejection Ratio Power Supply PSRR - 65 100 - 65 100 - 50 100 - dB Rejection Ratio Channel f = 1kHz to 20kHz CS - 120 - - 120 - - 120 - dB Separation (Note2) Short Circuit to ISC VCC = 15V - 40 60 - 40 60 - 40 60 mA GND VI(+) = 1V, VI(-) = 0V ISOURCE VCC = 15V 20 40 - 20 40 - 20 40 - mA VO(P) = 2V VI(+) = 0V, VI(-) = 1V Output Current VCC = 15V 10 13 - 10 13 - 10 13 - mA VO(P) = 2V ISINK VI(+) = 0V, VI(-) = 1V VCC = 5V,VO(R) = 12 45 - 12 45 - - - - µA 200mV Differential Input VI(DIFF) - - - VCC - - VCC - - VCC V Voltage Note : 1. VCC=30V for LM224 and LM324 , VCC = 26V for LM2902 2. This parameter, although guaranteed, is not 100% tested in production. 3 LM2902,LM324/LM324A,LM224/LM224A Electrical Characteristics (Continued) (VCC = 5.0V, VEE = GND, unless otherwise specified) The following specification apply over the range of -25°C ≤ TA ≤ + 85°C for the LM224; and the 0°C ≤ TA ≤ +70°C for the LM324 ; and the -40°C ≤ TA ≤ +85°C for the LM2902 LM224 LM324 LM2902 Parameter Symbol Conditions Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. VICM = 0V to VCC -1.5V Input Offset Voltage VIO - - 7.0 - - 9.0 - - 10.0 mV VO(P) = 1.4V, RS = 0Ω (Note1) Input Offset Voltage ∆VIO/∆T RS = 0Ω (Note2) - 7.0 - - 7.0 - - 7.0 - µV/°C Drift Input Offset Current IIO VCM = 0V - - 100 - - 150 - - 200 nA Input Offset Current ∆IIO/∆T RS = 0Ω (Note2) - 10 - - 10 - - 10 - pA/°C Drift Input Bias Current IBIAS VCM = 0V - - 300 - - 500 - - 500 nA Input Common-Mode VCC VCC VCC VI(R) Note1 0 - 0 - 0 - V Voltage Range -2.0 -2.0 -2.0 VCC = 15V, Large Signal Voltage GV RL = 2.0kΩ 25 - - 15 - - 15 - - V/mV Gain VO(P) = 1V to 11V RL=2kΩ 26 - - 26 - - 22 - - V VO(H) Note1 Output Voltage RL=10kΩ 27 28 - 27 28 - 23 24 - V Swing VCC = 5V, VO(L) - 5 20 - 5 20 - 5 100 mV RL=10kΩ VI(+) = 1V, VI(-) ISOURCE = 0V VCC = 15V, 10 20 - 10 20 - 10 20 - mA VO(P) = 2V Output Current VI(+) = 0V, VI(-) = 1V ISINK 10 13 - 5 8 - 5 8 - mA VCC = 15V, VO(P) = 2V Differential Input VI(DIFF) - - - VCC - - VCC - - VCC V Voltage Note: 1. VCC=30V for LM224 and LM324 , VCC = 26V for LM2902 2. These parameters, although guaranteed, are not 100% tested in production. 4 LM2902,LM324/LM324A,LM224/LM224A Electrical Characteristics (Continued) (VCC = 5.0V, VEE = GND, TA = 25°C, unless otherwise specified) LM224A LM324A Parameter Symbol Conditions Unit Min. Typ. Max. Min. Typ. Max. VCM = 0V to VCC -1.5V Input Offset Voltage VIO - 1.0 3.0 - 1.5 3.0 mV VO(P) = 1.4V, RS = 0Ω (Note1) Input Offset Current IIO VCM = 0V - 2 15 - 3.0 30 nA Input Bias Current IBIAS VCM = 0V - 40 80 - 40 100 nA VCC Input Common-Mode VCC VI(R) VCC = 30V 0 - 0 - -1.5 V Voltage Range -1.5 VCC = 30V, RL = ∞ - 1.5 3 - 1.5 3 mA Supply Current ICC VCC = 5V, RL = ∞ - 0.7 1.2 - 0.7 1.2 mA VCC = 15V, RL= 2kΩ Large Signal Voltage Gain GV 50 100 - 25 100 - V/mV VO(P) = 1V to 11V RL = 2kΩ 26 - - 26 - - V VO(H) Note1 Output Voltage Swing RL = 10kΩ 27 28 - 27 28 - V VO(L) VCC = 5V, RL=10kΩ - 5 20 - 5 20 mV Common-Mode Rejection CMRR - 70 85 - 65 85 - dB Ratio Power Supply Rejection Ratio PSRR - 65 100 - 65 100 - dB f = 1kHz to 20kHz Channel Separation CS - 120 - - 120 - dB (Note2) Short Circuit to GND ISC VCC = 15V - 40 60 - 40 60 mA VI(+) = 1V, VI(-) = 0V ISOURCE 20 40 - 20 40 - mA VCC =15V, VO(P) = 2V VI(+) = 0V, VI(-) = 1V 10 20 - 10 20 - mA Output Current VCC = 15V, VO(P) = 2V ISINK VI(+) = 0v, VI(-) = 1V VCC = 5V 12 50 - 12 50 - µA VO(P) = 200mV Differential Input Voltage VI(DIFF) - - - VCC - - VCC V Note: 1. VCC=30V for LM224A, LM324A 2. This parameter, although guaranteed, is not 100% tested in production. 5 LM2902,LM324/LM324A,LM224/LM224A Electrical Characteristics (Continued) (VCC = 5.0V, VEE = GND, unless otherwise specified) The following specification apply over the range of -25°C ≤ TA ≤ +85°C for the LM224A; and the 0°C ≤ TA ≤ +70°C for the LM324A LM224A LM324A Parameter Symbol Conditions Unit Min. Typ. Max. Min. Typ. Max. VCM = 0V to VCC -1.5V Input Offset Voltage VIO VO(P) = 1.4V, RS = 0Ω - - 4.0 - - 5.0 mV (Note1) Input Offset Voltage Drift ∆VIO/∆T RS = 0Ω (Note2) - 7.0 20 - 7.0 30 µV/°C Input Offset Current IIO VCM = 0V - - 30 - - 75 nA Input Offset Current Drift ∆IIO/∆T RS = 0Ω (Note2) - 10 200 - 10 300 pA/°C Input Bias Current IBIAS - - 40 100 - 40 200 nA Input Common-Mode VCC VCC VI(R) Note1 0 - 0 - V Voltage Range -2.0 -2.0 Large Signal Voltage Gain GV VCC = 15V, RL= 2.0kΩ 25 - - 15 - - V/mV RL = 2kΩ 26 - - 26 - - V VO(H) Note1 Output Voltage Swing RL = 10kΩ 27 28 - 27 28 - V VO(L) VCC = 5V, RL= 10kΩ - 5 20 - 5 20 mV VI(+) = 1V, VI(-) = 0V ISOURCE 10 20 - 10 20 - mA VCC = 15V, VO(P) = 2V Output Current VI(+) = 0V, VI(-) = 1V ISINK 5 8 - 5 8 - mA VCC = 15V, VO(P) = 2V Differential Input Voltage VI(DIFF) - - - VCC - - VCC V Note: 1. VCC=30V for LM224A and LM324A. 2. These parameters, although guaranteed, are not 100% tested in production. 6 LM2902,LM324/LM324A,LM224/LM224A Typical Performance Characteristics Temperature T ( j °C) Supply Voltage(v) Figure 1. Input Voltage Range vs Supply Voltage Figure 2. Input Current vs Temperature Supply Voltage (V) Supply Voltage (V) Figure 4. Voltage Gain vs Supply Voltage Figure 3. Supply Current vs Supply Voltage Frequency (Hz) Frequency (Hz) Figure 5. Open Loop Frequency Response Figure 6. Common mode Rejection Ratio 7 LM2902,LM324/LM324A,LM224/LM224A Typical Performance Characteristics (Continued) Figure 7. Voltage Follower Pulse Response Figure 8. Voltage Follower Pulse Response (Small Signal) Figure 8. Large Signal Frequency Response Figure 9. Output Characteristics vs Current Sourcing Figure 10. Output Characteristics vs Current Sinking Figure 11. Current Limiting vs Temperature 8 LM2902,LM324/LM324A,LM224/LM224A Mechanical Dimensions Package Dimensions in millimeters 14-DIP 6.40 ±0.20 0.252 ±0.008 #1 #14 #7 #8 7.62 0.300 3.25 ±0.20 0.20 0.128 ±0.008 0.008 MIN 5.08 3.30 ±0.30 0.200 MAX 0.130 ±0.012 +0.10 0.25 –0.05 +0.004 0~15° 0.010 –0.002 9 19.80 0.780 MAX 19.40 ±0.20 0.764 ±0.008 2.08 ( ) 0.082 0.46 ±0.10 2.54 0.018 ±0.004 0.100 1.50 ±0.10 0.059 ±0.004 LM2902,LM324/LM324A,LM224/LM224A Mechanical Dimensions (Continued) Package Dimensions in millimeters 14-SOP 0.05 MIN 0.002 1.55 ±0.10 0.061 ±0.004 #1 #14 #7 #8 6.00 ±0.30 1.80 0.236 ±0.012 0.071 MAX 3.95 ±0.20 0.156 ±0.008 5.72 0.225 0.60 ±0.20 0.024 ±0.008 10 +0.10 0.20 -0.05 +0.004 0.008 -0.002 0~8° 8.70 0.343 MAX 8.56 ±0.20 0.337 ±0.008 MAX0.10 MAX0.004 +0.10 0.406 -0.05 1.27 0.050 +0.004 0.47 0.016 ( )-0.002 0.019 LM2902,LM324/LM324A,LM224/LM224A Ordering Information Product Number Package Operating Temperature LM324N 14-DIP LM324AN 0 ~ +70°C LM324M 14-SOP LM324AM LM2902N 14-DIP -40 ~ +85°C LM2902M 14-SOP LM224N 14-DIP LM224AN -25 ~ +85°C LM224M 14-SOP LM224AM 11 LM2902,LM324/LM324A,LM224/LM224A DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 11/19/02 0.0m 001 Stock#DSxxxxxxxx  2002 Fairchild Semiconductor Corporation This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components. AILABLE MAX220–MAX249 AV +5V-Powered, Multichannel RS-232 Drivers/Receivers General Description Next-Generation Device Features The MAX220–MAX249 family of line drivers/receivers is ♦ For Low-Voltage, Integrated ESD Applications intended for all EIA/TIA-232E and V.28/V.24 communica- MAX3222E/MAX3232E/MAX3237E/MAX3241E/ tions interfaces, particularly applications where ±12V is MAX3246E: +3.0V to +5.5V, Low-Power, Up to not available. 1Mbps, True RS-232 Transceivers Using Four These parts are especially useful in battery-powered sys- 0.1µF External Capacitors (MAX3246E Available tems, since their low-power shutdown mode reduces in a UCSP™ Package) power dissipation to less than 5µW. The MAX225, ♦ For Low-Cost Applications MAX233, MAX235, and MAX245/MAX246/MAX247 use MAX221E: ±15kV ESD-Protected, +5V, 1µA, no external components and are recommended for appli- Single RS-232 Transceiver with AutoShutdown™ cations where printed circuit board space is critical. Ordering Information ________________________Applications PART TEMP RANGE PIN-PACKAGE Portable Computers MAX220CPE+ 0°C to +70°C 16 Plastic DIP MAX220CSE+ 0°C to +70°C 16 Narrow SO Low-Power Modems MAX220CWE+ 0°C to +70°C 16 Wide SO Interface Translation MAX220C/D 0°C to +70°C Dice* Battery-Powered RS-232 Systems MAX220EPE+ -40°C to +85°C 16 Plastic DIP Multidrop RS-232 Networks MAX220ESE+ -40°C to +85°C 16 Narrow SO MAX220EWE+ -40°C to +85°C 16 Wide SO MAX220EJE -40°C to +85°C 16 CERDIP MAX220MJE -55°C to +125°C 16 CERDIP +Denotes a lead(Pb)-free/RoHS-compliant package. *Contact factory for dice specifications. AutoShutdown and UCSP are trademarks of Maxim Integrated Products, Inc. Ordering Information continued at end of data sheet. Selection Table Power No. of Nominal SHDN Rx Part Supply RS-232 No. of Cap. Value & Three- Active in Data Rate Number (V) FunDcrivteriso/Rnx aExlt. CDapisag(µFr)amsState SHDN (kbps) FeaturesMAX220 +5 2/2 4 0.047/0.33 No — 120 Ultra-low-power, industry-standard pinout MAX222 +5 2/2 4 0.1 Yes — 200 Low-power shutdown MAX223 (MAX213) +5 4/5 4 1.0 (0.1) Yes ✔ 120 MAX241 and receivers active in shutdown MAX225 +5 5/5 0 — Yes ✔ 120 Available in SO MAX230 (MAX200) +5 5/0 4 1.0 (0.1) Yes — 120 5 drivers with shutdown MAX231 (MAX201) +5 and 2/2 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies; +7.5 to +13.2 same functions as MAX232 MAX232 (MAX202) +5 2/2 4 1.0 (0.1) No — 120 (64) Industry standard MAX232A +5 2/2 4 0.1 No — 200 Higher slew rate, small caps MAX233 (MAX203) +5 2/2 0 — No — 120 No external caps MAX233A +5 2/2 0 — No — 200 No external caps, high slew rate MAX234 (MAX204) +5 4/0 4 1.0 (0.1) No — 120 Replaces 1488 MAX235 (MAX205) +5 5/5 0 — Yes — 120 No external caps MAX236 (MAX206) +5 4/3 4 1.0 (0.1) Yes — 120 Shutdown, three state MAX237 (MAX207) +5 5/3 4 1.0 (0.1) No — 120 Complements IBM PC serial port MAX238 (MAX208) +5 4/4 4 1.0 (0.1) No — 120 Replaces 1488 and 1489 MAX239 (MAX209) +5 and 3/5 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies; +7.5 to +13.2 single-package solution for IBM PC serial port MAX240 +5 5/5 4 1.0 Yes — 120 DIP or flatpack package MAX241 (MAX211) +5 4/5 4 1.0 (0.1) Yes — 120 Complete IBM PC serial port MAX242 +5 2/2 4 0.1 Yes ✔ 200 Separate shutdown and enable MAX243 +5 2/2 4 0.1 No — 200 Open-line detection simplifies cabling MAX244 +5 8/10 4 1.0 No — 120 High slew rate MAX245 +5 8/10 0 — Yes ✔ 120 High slew rate, int. caps, two shutdown modes PMinA CX2o4n6figurations+ 5appear at e8n/1d0 of data0 sheet. — Yes ✔ 120 High slew rate, int. caps, three shutdown modes FMunAcXt2i4o7nal Diagram+5s continue8d/9 at end of0 data shee—t. Yes ✔ 120 High slew rate, int. caps, nine operating modes MAX248 +5 8/8 4 1.0 Yes ✔ 120 High slew rate, selective half-chip enables UMCASXP2 4is9 a trademar+k5 of Maxim I6n/t1e0grated P4roducts, In1c.0. Yes ✔ 120 Available in quad flatpack package For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-4323; Rev 16; 7/10 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ABSOLUTE MAXIMUM RATINGS—MAX220/222/232A/233A/242/243 (Voltages referenced to GND.) 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW VCC...........................................................................-0.3V to +6V 16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW V+ (Note 1) ..................................................(VCC - 0.3V) to +14V 18-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW V- (Note 1) ..............................................................+0.3V to -14V 20-Pin Wide SO (derate 10.00mW/°C above +70°C)....800mW Input Voltages 20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW TIN .............................................................-0.3V to (VCC - 0.3V) 16-Pin CERDIP (derate 10.00mW/°C above +70°C).....800mW RIN (Except MAX220) ........................................................±30V 18-Pin CERDIP (derate 10.53mW/°C above +70°C).....842mW RIN (MAX220) ....................................................................±25V Operating Temperature Ranges TOUT (Except MAX220) (Note 2) ......................................±15V MAX2_ _AC_ _, MAX2_ _C_ _.............................0°C to +70°C TOUT (MAX220)..............................................................±13.2V MAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40°C to +85°C Output Voltages MAX2_ _AM_ _, MAX2_ _M_ _.......................-55°C to +125°C TOUT..................................................................................±15V Storage Temperature Range .............................-65°C to +160°C ROUT........................................................-0.3V to (VCC + 0.3V) Lead Temperature (soldering, 10s) .................................+300°C Driver/Receiver Output Short Circuited to GND.........Continuous Soldering Temperature (reflow) Continuous Power Dissipation (TA = +70°C) 20 PDIP (P20M+1) .......................................................+225°C 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW All other lead(Pb)-free packages.................................+260°C 18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)..889mW All other packages containing lead(Pb) ......................+240°C 20-Pin Plastic DIP (derate 8.00mW/°C above +70°C) ..440mW Note 1: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V. Note 2: Input voltage measured with TOUT in high-impedance state, VSHDN or VCC = 0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS RS-232 TRANSMITTERS Output Voltage Swing All transmitter outputs loaded with 3k to GND ±5 ±8 V Input Logic-Low Voltage 1.4 0.8 V All devices except MAX220 2 1.4 Input Logic-High Voltage V MAX220: VCC = +5.0V 2.4 All except MAX220, normal operation 5 40 Logic Pullup/lnput Current VSHDN = 0V, MAX222/MAX242, shutdown, μA ±0.01 ±1 MAX220 VCC = +5.5V, VSHDN = 0V, VOUT = ±15V, ±0.01 ±10 MAX222/MAX242 Output Leakage Current μA VOUT = ±15V ±0.01 ±10 VCC = VSHDN = 0V MAX220, VOUT = ±12V ±25 Data Rate 200 116 kbps Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M VOUT = 0V ±7 ±22 Output Short-Circuit Current VOUT = 0V mA MAX220 ±60 RS-232 RECEIVERS ±30 RS-232 Input Voltage Operating Range V MAX220 ±25 All except MAX243 R2IN 0.8 1.3 RS-232 Input Threshold Low VCC = +5V V MAX243 R2IN (Note 4) -3 All except MAX243 R2IN 1.8 2.4 RS-232 Input Threshold High VCC = +5V V MAX243 R2IN (Note 4) -0.5 -0.1 2 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued) (VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS All except MAX220/MAX243, VCC = +5V, no 0.2 0.5 1.0 hysteresis in shutdown RS-232 Input Hysteresis V MAX220 0.3 MAX243 1 3 5 7 RS-232 Input Resistance TA = +25°C (MAX220) k 3 5 7 IOUT = 3.2mA 0.2 0.4 TTL/CMOS Output Voltage Low V IOUT = 1.6mA (MAX220) 0.4 TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V Sourcing VOUT = VGND -2 -10 TTL/CMOS Output Short-Circuit Current mA Sinking VOUT = VCC 10 30 V = V or V = V (V = 0V for TTL/CMOS Output Leakage Current SHDN CC EN CC SHDN ±0.05 ±10 μA MAX222), 0V VOUT VCC EN Input Threshold Low MAX242 1.4 0.8 V EN Input Threshold High MAX242 2.0 1.4 V Supply Voltage Range 4.5 5.5 V MAX220 0.5 2 No load MAX222/MAX232A/MAX233A/ 4 10 VCC Supply Current (VSHDN = VCC), MAX242/MAX243 mA Figures 5, 6, 11, 19 MAX220 12 3k load both inputs MAX222/MAX232A/MAX233A/ 15 MAX242/MAX243 TA = +25°C 0.1 10 MAX222/ TA = 0°C to +70°C 2 50 Shutdown Supply Current μA MAX242 TA = -40°C to +85°C 2 50 TA = -55°C to +125°C 35 100 SHDN Input Leakage Current MAX222/MAX242 ±1 μA SHDN Threshold Low MAX222/MAX242 1.4 0.8 V SHDN Threshold High MAX222/MAX242 2.0 1.4 V CL = 50pF to 2500pF, MAX222/MAX232A/ RL = 3k to 7k , 6 12 30 MAX233/MAX242/MAX243 VCC = +5V, TTransition Slew Rate A = V/μs +25°C, measured from +3V to -3V or MAX220 1.5 3 30.0 -3V to +3V MAX222/MAX232A/ 1.3 3.5 tPHLT, Figure 1 MAX233/MAX242/MAX243 Transmitter Propagation Delay TLL to MAX220 4 10 μs RS-232 (Normal Operation) MAX222/MAX232A/ 1.5 3.5 tPLHT, Figure 1 MAX233/MAX242/MAX243 MAX220 5 10 Maxim Integrated 3 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued) (VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS MAX222/MAX232A/MAX233/ 0.5 1 tPHLR, Figure 2 MAX242/MAX243 Receiver Propagation Delay RS-232 to MAX220 0.6 3 μs TLL (Normal Operation) MAX222/MAX232A/MAX233/ 0.6 1 tPLHR, Figure 2 MAX242/MAX243 MAX220 0.8 3 Receiver Propagation Delay RS-232 to tPHLS, Figure 2 MAX242 0.5 10 μs TLL (Shutdown) tPHLS, Figure 2 MAX242 2.5 10 Receiver-Output Enable Time tER MAX242, Figure 3 125 500 ns Receiver-Output Disable Time tDR MAX242, Figure 3 160 500 ns MAX222/MAX242, 0.1μF Transmitter-Output Enable Time t caps (includes charge-pump 250 μs (SHDN Goes High) ET start-up), Figure 4 Transmitter-Output Disable Time MAX222/MAX242, t 600 ns (SHDN Goes Low) DT 0.1μF caps, Figure 4 MAX222/MAX232A/MAX233/ Transmitter + to - Propagation Delay 300 t Difference (Normal Operation) PHLT - tPLHT MAX242/MAX243 ns MAX220 2000 MAX222/MAX232A/MAX233/ Receiver + to - Propagation Delay 100 t - t MAX242/MAX243 ns Difference (Normal Operation) PHLR PLHR MAX220 225 Note 3: All units are production tested at hot. Specifications over temperature are guaranteed by design. Note 4: MAX243 R2OUT is guaranteed to be low when R2IN ≥ 0V or is unconnected. __________________________________________Typical Operating Characteristics MAX220/MAX222/MAX232A/MAX233A/MAX242/MAX243 AVAILABLE OUTPUT CURRENT MAX222/MAX242 OUTPUT VOLTAGE vs. LOAD CURRENT vs. DATA RATE ON-TIME EXITING SHUTDOWN 10 11 +10V 1μF 8 OUTPUT LOAD CURRENT V+ 1μF CAPS EITHER V+ OR V- LOADED 10 FLOWS FROM V+ TO V-6 V+ +5V 0.1μF CAPS 4 VCC = +5V 0.1μF ALL CAPS 9 1μF +5V NO LOAD ON SHDN 2 TRANSMITTER OUTPUTS VCC = +5.25V8 0V 0 (EXCEPT MAX220, MAX233A) 0V ALL CAPS -2 V- LOADED, NO LOAD ON V+ 7 0.1μF V μ 1μF CC = +4.75V -4 0.1 F 1μF CAPS 6 -6 5 0.1μF CAPS -8 V- V+ LOADED, NO LOAD ON V- V- -10 4 -10V 0 5 10 15 20 25 0 10 20 30 40 50 60 500μs/div LOAD CURRENT (mA) DATA RATE (kb/s) 4 Maxim Integrated OUTPUT VOLTAGE (V) MAX220-01 OUTPUT CURRENT (mA) MAX220-02 V+, V- VOLTAGE (V) MAX220-03 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ABSOLUTE MAXIMUM RATINGS—MAX223/MAX230–MAX241 (Voltages referenced to GND.) 28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W VCC...........................................................................-0.3V to +6V 44-Pin Plastic FP (derate 11.11mW/°C above +70°C) .....889mW V+................................................................(VCC - 0.3V) to +14V 14-Pin CERDIP (derate 9.09mW/°C above +70°C) ..........727mW V- ............................................................................+0.3V to -14V 16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW Input Voltages 20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW TIN............................................................-0.3V to (VCC + 0.3V) 24-Pin Narrow CERDIP RIN .....................................................................................±30V (derate 12.50mW/°C above +70°C) ..............1W Output Voltages 24-Pin Sidebraze (derate 20.0mW/°C above +70°C)..........1.6W TOUT ..................................................(V+ + 0.3V) to (V- - 0.3V) 28-Pin SSOP (derate 9.52mW/°C above +70°C).............762mW ROUT........................................................-0.3V to (VCC + 0.3V) Operating Temperature Ranges Short-Circuit Duration, TOUT to GND ........................Continuous MAX2 _ _ C _ _......................................................0°C to +70°C Continuous Power Dissipation (TA = +70°C) MAX2 _ _ E _ _ ...................................................-40°C to +85°C 14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)....800mW MAX2 _ _ M _ _......................................................-55°C to +125°C 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW Storage Temperature Range .............................-65°C to +160°C 20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW Lead Temperature (soldering, 10s) .................................+300°C 24-Pin Narrow Plastic DIP Soldering Temperature (reflow) (derate 13.33mW/°C above +70°C) ..........1.07W 20 PDIP (P20M+1) .........................................................+225°C 24-Pin Plastic DIP (derate 9.09mW/°C above +70°C)......500mW 24 PDIP (P24M-1) ..........................................................+225°C 16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW All other lead(Pb)-free packages...................................+260°C 20-Pin Wide SO (derate 10.00mW/°C above +70°C).......800mW All other packages containing lead(Pb) ...........................+240°C 24-Pin Wide SO (derate 11.76mW/°C above +70°C).......941mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10%; MAX233/MAX235, VCC = +5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239, VCC = +5V ±10%; V+ = +7.5V to +13.2V; TA = TMIN to TMAX; unless otherwise noted.) (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±7.3 V MAX232/233 5 10 No load, VCC Supply Current MAX223/230/234–238/240/241 7 15 mATA = +25°C MAX231/239 0.4 1 MAX231 1.8 5 V+ Supply Current mA MAX239 5 15 MAX223 15 50 Shutdown Supply Current TA = +25°C µA MAX230/235/236/240/241 1 10 Input Logic-Low Voltage TIN, EN, SHDN (MAX233); EN, SHDN (MAX230/235–241) 0.8 V TIN 2.0 Input Logic-High Voltage EN, SHDN (MAX223); V 2.4 EN, SHDN (MAX230/235/236/240/241) Logic Pullup Current VTIN = 0V 1.5 200 µA Receiver Input Voltage -30 +30 V Operating Range Maxim Integrated 5 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (continued) (MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10%; MAX233/MAX235, VCC = +5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239, VCC = +5V ±10%; V+ = +7.5V to +13.2V; TA = TMIN to TMAX; unless otherwise noted.) (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Normal operation VSHDN = +5V (MAX223) 0.8 1.2 T = +25°C, VSHDN = 0V (MAX235/236/240/241) RS-232 Input Logic-Low Voltage A V VCC = +5V Shutdown (MAX223) VSHDN = 0V, 0.6 1.5 VEN = +5V (R4IN, R5IN) Normal operation VSHDN = 5V (MAX223) 1.7 2.4 TA = +25°C, VSHDN = 0V (MAX235/236/240/241)RS-232 Input Logic-High Voltage V VCC = +5V Shutdown (MAX223) VSHDN = 0V, 1.5 2.4 VEN = +5V (R4IN‚ R5IN) RS-232 Input Hysteresis VCC = +5V, no hysteresis in shutdown 0.2 0.5 1.0 V RS-232 Input Resistance TA = +25°C, VCC = +5V 3 5 7 kΩ TTL/CMOS Output Voltage Low IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA) 0.4 V TTL/CMOS Output Voltage High IOUT = -1mA 3.5 VCC - 0.4 V 0V ≤ R ≤ V ; V = 0V (MAX223); TTL/CMOS Output Leakage Current OUT CC EN ±0.05 ±10 µA VEN = VCC (MAX235–241) Normal MAX223 600 Receiver Output Enable Time ns operation MAX235/236/239/240/241 400 Normal MAX223 900 Receiver Output Disable Time ns operation MAX235/236/239/240/241 250 RS-232 IN to Normal operation 0.5 10 Propagation Delay TTL/CMOS OUT, VSHDN = 0V tPHLS 4 40 µs CL = 150pF (MAX223) tPLHS 6 40 MAX223/MAX230/MAX234–241, TA = +25°C, VCC = +5V, RL = 3kΩ to 7kΩ‚ CL = 50pF to 2500pF, measured from 3 5.1 30 +3V to -3V or -3V to +3V Transition Region Slew Rate V/µs MAX231/MAX232/MAX233, TA = +25°C, VCC = +5V, RL = 3kΩ to 7kΩ, CL = 50pF to 2500pF, measured from 4 30 +3V to -3V or -3V to +3V Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 Ω Transmitter Output Short-Circuit ±10 mA Current mA Note 5: All units are production tested at hot except for the MAX240, which is production tested at TA = +25°C. Specifications over temperature are guaranteed by design. 6 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers __________________________________________Typical Operating Characteristics MAX223/MAX230–MAX241 TRANSMITTER OUTPUT VOLTAGE (VOH) TRANSMITTER OUTPUT vs. LOAD CAPACITANCE AT TRANSMITTER SLEW RATE VOLTAGE (VOH) vs. VCC DIFFERENT DATA RATES vs. LOAD CAPACITANCE 8.5 7.4 12.0 1 TRANSMITTER LOADED TA = +25°C2 TRANSMITTERS 11.0 V = +5V LOADED 7.2 CCLOADED, RL = 3kΩ 8.0 10.07.0 C1–C4 = 1μF 1 TRANSMITTER 9.0 2 TRANSMITTERS LOADED 6.8 160kb/s LOADED 7.5 3 TRANS- 80kb/s 8.0 MITTERS 6.6 20kb/s LOADED 7.0 TA = +25°C 6.4 TA = +25°C 6.0 3 TRANSMITTERS7.0 C1–C4 = 1μF VCC = +5V LOADED TRANSMITTER 6.2 3 TRANSMITTERS LOADED 4 TRANSMITTERS 4 TRANSMITTERS LOADS = RL = 3kΩ 5.0 C1–C4 = 1μF LOADEDLOADED 3kΩ || 2500pF6.5 6.0 4.0 4.5 5.0 5.5 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500 VCC (V) LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (VOL) TRANSMITTER OUTPUT vs. LOAD CAPACITANCE AT TRANSMITTER OUTPUT VOLTAGE (V+, V-) VOLTAGE (VOL) vs. VCC DIFFERENT DATA RATES vs. LOAD CURRENT -6.0 -6.0 10 4 TRANS- TA = +25°C T = +25°C MITTERS C1–C4 = 1μF A -6.5 -6.2 8 VCC = +5VLOADED TRANSMITTER 3 TRANSMITTERS LOADED 6 LOADS = T = +25°C-6.4 AR = 3kΩ -7.0 3kΩ || 2500pF L VCC = +5V C1–C4 = 1μF 4 -6.6 C1–C4 = 1μF2 V+ AND V- V- LOADED, -7.5 160kb/s NO LOAD V+ LOADED,-6.8 80kb/s 0 EQUALLY NO LOAD 1 TRANS- 20kb/s -2 LOADED ON V+ -7.0 ON V- -8.0 MITTER LOADED -4-7.2 -8.5 2 TRANS- 3 TRANS- -6 MITTERS MITTERS -7.4 LOADED LOADED -8 -9.0 ALL TRANSMITTERS UNLOADED-7.6 -10 4.5 5.0 5.5 0 500 1000 1500 2000 2500 0 5 10 15 20 25 30 35 40 45 50 VCC (V) LOAD CAPACITANCE (pF) CURRENT (mA) V+, V- WHEN EXITING SHUTDOWN (1μF CAPACITORS) MAX220-13 V+ O V- VSHDN* 500ms/div *SHUTDOWN POLARITY IS REVERSED Maxim Integrated 7 VOL (V) VOH (V) MAX220-07 MAX220-04 VOL (V) VOH (V) MAX220-08 MAX220-05 V+, V- (V) SLEW RATE (V/μs) MAX220-09 MAX220-06 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ABSOLUTE MAXIMUM RATINGS—MAX225/MAX244–MAX249 (Voltages referenced to GND.) Continuous Power Dissipation (TA = +70°C) Supply Voltage (VCC) ...............................................-0.3V to +6V 28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W Input Voltages 40-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ...611mW TIN‚ ENA, ENB, ENR, ENT, ENRA, 44-Pin PLCC (derate 13.33mW/°C above +70°C) ...........1.07W ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V) Operating Temperature Ranges RIN.....................................................................................±25V MAX225C_ _, MAX24_C_ _ ..................................0°C to +70°C TOUT (Note 6)....................................................................±15V MAX225E_ _, MAX24_E_ _ ...............................-40°C to +85°C ROUT........................................................-0.3V to (VCC + 0.3V) Storage Temperature Range .............................-65°C to +160°C Short Circuit Duration (one output at a time) Lead Temperature (soldering,10s)) .................................+300°C TOUT to GND...........................................................Continuous Soldering Temperature (reflow) ROUT to GND...........................................................Continuous 40 PDIP (P40M-2) ..........................................................+225°C All other lead(Pb)-free packages...................................+260°C All other packages containing lead(Pb) ........................+240°C Note 6: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (MAX225, VCC = +5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless otherwise noted.) (Note 7) PARAMETER CONDITIONS MIN TYP MAX UNITS RS-232 TRANSMITTERS Input Logic-Low Voltage 1.4 0.8 V Input Logic-High Voltage 2 1.4 V Normal operation 10 50 Logic Pullup/lnput Current Tables 1a–1d µA Shutdown ±0.01 ±1 Data Rate Tables 1a–1d, normal operation 120 64 kbps Output Voltage Swing All transmitter outputs loaded with 3kΩ to GND ±5 ±7.5 V VENA, VENB, VENT, VENTA, ±0.01 ±25 VENTB = VCC, VOUT = ±15V Output Leakage Current (Shutdown) Tables 1a–1d µA VCC = 0V, ±0.01 ±25 VOUT = ±15V Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V (Note 8) 300 10M Ω Output Short-Circuit Current VOUT = 0V ±7 ±30 mA RS-232 RECEIVERS RS-232 Input Voltage Operating Range ±25 V RS-232 Input Logic-Low Voltage VCC = +5V 0.8 1.3 V RS-232 Input Logic-High Voltage VCC = +5V 1.8 2.4 V RS-232 Input Hysteresis VCC = +5V 0.2 0.5 1.0 V RS-232 Input Resistance 3 5 7 kΩ TTL/CMOS Output Voltage Low IOUT = 3.2mA 0.2 0.4 V TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V Sourcing VOUT = VGND -2 -10 TTL/CMOS Output Short-Circuit Current mA Sinking VOUT = VCC 10 30 Normal operation, outputs disabled, TTL/CMOS Output Leakage Current ≤ ≤ ±0.05 ±0.10 µATables 1a–1d, 0V VOUT VCC, VENR_ = VCC 8 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (continued) (MAX225, VCC = +5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless otherwise noted.) (Note 7) PARAMETER CONDITIONS MIN TYP MAX UNITS POWER SUPPLY AND CONTROL LOGIC MAX225 4.75 5.25 Supply Voltage Range V MAX244–MAX249 4.5 5.5 MAX225 10 20 No load VCC Supply Current MAX244–MAX249 11 30 mA (Normal Operation) 3kΩ loads on MAX225 40 all outputs MAX244–MAX249 57 TA = +25°C 8 25 Shutdown Supply Current µA TA = TMIN to TMAX 50 Leakage current ±1 µA Control Input Logic-low voltage 1.4 0.8 V Logic-high voltage 2.4 1.4 AC CHARACTERISTICS C = 50pF to 2500pF, R = 3kΩ to 7kΩ, V = +5V, Transition Slew Rate L L CC 5 10 30 V/µs TA = +25°C, measured from +3V to -3V or -3V to +3V Transmitter Propagation Delay tPHLT, Figure 1 1.3 3.5 µs TLL to RS-232 (Normal Operation) tPLHT, Figure 1 1.5 3.5 Receiver Propagation Delay tPHLR, Figure 2 0.6 1.5 µs TLL to RS-232 (Normal Operation) tPLHR, Figure 2 0.6 1.5 Receiver Propagation Delay tPHLS, Figure 2 0.6 10 µs TLL to RS-232 (Low-Power Mode) tPLHS, Figure 2 3.0 10 Transmitter + to - Propagation tPHLT - tPLHT 350 nsDelay Difference (Normal Operation) Receiver + to - Propagation tPHLR - tPLHR 350 nsDelay Difference (Normal Operation) Receiver-Output Enable Time tER, Figure 3 100 500 ns Receiver-Output Disable Time tDR, Figure 3 100 500 ns MAX246–MAX249 5 µs (excludes charge-pump startup) Transmitter Enable Time tET MAX225/MAX245–MAX249 10 ms (includes charge-pump startup) Transmitter Disable Time tDT, Figure 4 100 ns Note 7: All units production tested at hot. Specifications over temperature are guaranteed by design. Note 8: The 300Ω minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC = 0V is 10MΩ as is implied by the leakage specification. Maxim Integrated 9 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers __________________________________________Typical Operating Characteristics MAX225/MAX244–MAX249 TRANSMITTER OUTPUT VOLTAGE (V+, V-) TRANSMITTER SLEW RATE OUTPUT VOLTAGE vs. LOAD CAPACITANCE AT vs. LOAD CAPACITANCE vs. LOAD CURRENT FOR V+ AND V- DIFFERENT DATA RATES 18 10 9.0 VCC = +5V WITH ALL TRANSMITTERS DRIVENVCC = +5V 16 8 LOADED WITH 5kΩV+ AND V- LOADED 8.5 6 10kb/sEITHER V+ OR 14 8.0 20kb/s EXTERNAL POWER SUPPLY 4 VCC = +5V V- LOADED 12 1μF CAPACITORS 2 EXTERNAL CHARGE PUMP 7.5 40kb/s 1μF CAPACITORS 10 0 8 TRANSMITTERS 7.0 60kb/s 40kb/s DATA RATE DRIVING 5kΩ AND 8 8 TRANSMITTERS -2 2000pF AT 20kb/s 6.5 LOADED WITH 3kΩ -4 V- LOADED 6 6.0 100kb/s -6 V+ AND V- LOADED 200kb/s 4 -8 5.5 V+ LOADED ALL CAPACITIORS 1μF 2 -10 5.0 0 1 2 3 4 5 0 5 10 15 20 25 30 35 0 1 2 3 4 5 LOAD CAPACITANCE (nF) LOAD CURRENT (mA) LOAD CAPACITANCE (nF) 10 Maxim Integrated TRANSMITTER SLEW RATE (V/μs) MAX220-10 OUTPUT VOLTAGE (V) MAX220-11 V+, V- (V) MAX220-12 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers Test Circuits/Timing Diagrams +3V 0V* 50% 50% +3V INPUT INPUT 0V VCC OUTPUT 50% 50% V+ GND OUTPUT 0V V- tPHLR tPLHR tPHLS tPLHS tPLHT tPHLT *EXCEPT FOR R2 ON THE MAX243 WHERE -3V IS USED. Figure 1. Transmitter Propagation-Delay Timing Figure 2. Receiver Propagation-Delay Timing EN RX OUT 1kΩ RX IN RX VCC - 2V +3V SHDN a) TEST CIRCUIT 0V 150pF +3V OUTPUT DISABLE TIME (tDT) EN INPUT 0V V+EN +5V OUTPUT ENABLE TIME (tER) 0V +3.5V -5V RECEIVER V- OUTPUTS +0.8V a) TIMING DIAGRAM b) ENABLE TIMING +3V EN 0V EN INPUT 1 OR 0 TX OUTPUT DISABLE TIME (tDR) 3kΩ 50pF VOH VOH - 0.5V RECEIVER VCC - 2V OUTPUTS VOL + 0.5V b) TEST CIRCUIT VOL c) DISABLE TIMING Figure 3. Receiver-Output Enable and Disable Timing Figure 4. Transmitter-Output Disable Timing Maxim Integrated 11 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers Control Pin Configuration Tables Table 1a. MAX245 Control Pin Configurations ENT ENR OPERATION STATUS TRANSMITTERS RECEIVERS 0 0 Normal Operation All Active All Active 0 1 Normal Operation All Active All High-Z 1 0 Shutdown All High-Z All Low-Power Receive Mode 1 1 Shutdown All High-Z All High-Z Table 1b. MAX245 Control Pin Configurations OPERATION TRANSMITTERS RECEIVERS ENT ENR STATUS TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5 0 0 Normal Operation All Active All Active All Active All Active RA1–RA4 High-Z, RB1–RB4 High-Z, 0 1 Normal Operation All Active All Active RA5 Active RB5 Active All Low-Power All Low-Power 1 0 Shutdown All High-Z All High-Z Receive Mode Receive Mode RA1–RA4 High-Z, RB1–RB4 High-Z, 1 1 Shutdown All High-Z All High-Z RA5 Low-Power RB5 Low-Power Receive Mode Receive Mode Table 1c. MAX246 Control Pin Configurations OPERATION TRANSMITTERS RECEIVERS ENA ENB STATUS TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5 0 0 Normal Operation All Active All Active All Active All Active RB1–RB4 High-Z, 0 1 Normal Operation All Active All High-Z All Active RB5 Active RA1–RA4 High-Z, 1 0 Shutdown All High-Z All Active All Active RA5 Active RA1–RA4 High-Z, RB1–RB4 High-Z, 1 1 Shutdown All High-Z All High-Z RA5 Low-Power RA5 Low-Power Receive Mode Receive Mode 12 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations TRANSMITTERS RECEIVERS OPERATION MAX247 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB5 ENTA ENTB ENRA ENRB STATUS MAX248 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB4 MAX249 TA1–TA3 TB1–TB3 RA1–RA5 RB1–RB5 0 0 0 0 Normal Operation All Active All Active All Active All Active All High-Z, except 0 0 0 1 Normal Operation All Active All Active All Active RB5 stays active on MAX247 0 0 1 0 Normal Operation All Active All Active All High-Z All Active All High-Z, except 0 0 1 1 Normal Operation All Active All Active All High-Z RB5 stays active on MAX247 0 1 0 0 Normal Operation All Active All High-Z All Active All Active All High-Z, except 0 1 0 1 Normal Operation All Active All High-Z All Active RB5 stays active on MAX247 0 1 1 0 Normal Operation All Active All High-Z All High-Z All Active All High-Z, except 0 1 1 1 Normal Operation All Active All High-Z All High-Z RB5 stays active on MAX247 1 0 0 0 Normal Operation All High-Z All Active All Active All Active All High-Z, except 1 0 0 1 Normal Operation All High-Z All Active All Active RB5 stays active on MAX247 1 0 1 0 Normal Operation All High-Z All Active All High-Z All Active All High-Z, except 1 0 1 1 Normal Operation All High-Z All Active All High-Z RB5 stays active on MAX247 Low-Power Low-Power 1 1 0 0 Shutdown All High-Z All High-Z Receive Mode Receive Mode All High-Z, except Low-Power 1 1 0 1 Shutdown All High-Z All High-Z RB5 stays active on Receive Mode MAX247 Low-Power 1 1 1 0 Shutdown All High-Z All High-Z All High-Z Receive Mode All High-Z, except 1 1 1 1 Shutdown All High-Z All High-Z All High-Z RB5 stays active on MAX247 Maxim Integrated 13 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers _______________Detailed Description mode, in three-state mode, or when device power is removed. Outputs can be driven to ±15V. The power- The MAX220–MAX249 contain four sections: dual supply current typically drops to 8µA in shutdown mode. charge-pump DC-DC voltage converters, RS-232 dri- The MAX220 does not have pullup resistors to force the vers, RS-232 receivers, and receiver and transmitter outputs of the unused drivers low. Connect unused enable control inputs. inputs to GND or VCC. Dual Charge-Pump Voltage Converter The MAX239 has a receiver three-state control line, and The MAX220–MAX249 have two internal charge-pumps the MAX223, MAX225, MAX235, MAX236, MAX240, that convert +5V to ±10V (unloaded) for RS-232 driver and MAX241 have both a receiver three-state control operation. The first converter uses capacitor C1 to dou- line and a low-power shutdown control. Table 2 shows ble the +5V input to +10V on C3 at the V+ output. The the effects of the shutdown control and receiver three- second converter uses capacitor C2 to invert +10V to state control on the receiver outputs. -10V on C4 at the V- output. The receiver TTL/CMOS outputs are in a high-imped- A small amount of power may be drawn from the +10V ance, three-state mode whenever the three-state enable (V+) and -10V (V-) outputs to power external circuitry line is high (for the MAX225/MAX235/MAX236/MAX239– (see the Typical Operating Characteristics section), MAX241), and are also high-impedance whenever the except on the MAX225 and MAX245–MAX247, where shutdown control line is high. these pins are not available. V+ and V- are not regulated, When in low-power shutdown mode, the driver outputs so the output voltage drops with increasing load current. are turned off and their leakage current is less than 1µA Do not load V+ and V- to a point that violates the mini- with the driver output pulled to ground. The driver output mum ±5V EIA/TIA-232E driver output voltage when leakage remains less than 1µA, even if the transmitter sourcing current from V+ and V- to external circuitry. output is backdriven between 0V and (VCC + 6V). Below When using the shutdown feature in the MAX222, -0.5V, the transmitter is diode clamped to ground with MAX225, MAX230, MAX235, MAX236, MAX240, 1kΩ series impedance. The transmitter is also zener MAX241, and MAX245–MAX249, avoid using V+ and V- clamped to approximately VCC + 6V, with a series to power external circuitry. When these parts are shut impedance of 1kΩ. down, V- falls to 0V, and V+ falls to +5V. For applica- The driver output slew rate is limited to less than 30V/µs tions where a +10V external supply is applied to the V+ as required by the EIA/TIA-232E and V.28 specifica- pin (instead of using the internal charge pump to gen- tions. Typical slew rates are 24V/µs unloaded and erate +10V), the C1 capacitor must not be installed and 10V/µs loaded with 3Ω and 2500pF. the SHDN pin must be connected to VCC. This is because V+ is internally connected to VCC in shutdown RS-232 Receivers mode. EIA/TIA-232E and V.28 specifications define a voltage level greater than 3V as a logic 0, so all receivers invert. RS-232 Drivers Input thresholds are set at 0.8V and 2.4V, so receivers The typical driver output voltage swing is ±8V when respond to TTL level inputs as well as EIA/TIA-232E and loaded with a nominal 5kΩ RS-232 receiver and VCC = V.28 levels. +5V. Output swing is guaranteed to meet the EIA/TIA- 232E and V.28 specification, which calls for ±5V mini- The receiver inputs withstand an input overvoltage up mum driver output levels under worst-case conditions. to ±25V and provide input terminating resistors with These include a minimum 3kΩ load, VCC = +4.5V, and maximum operating temperature. Unloaded driver out- Table 2. Three-State Control of Receivers put voltage ranges from (V+ -1.3V) to (V- +0.5V). PART SHDN SHDN EN EN(R) RECEIVERS Input thresholds are both TTL and CMOS compatible. The inputs of unused drivers can be left unconnected Low X High Impedance since 400kΩ input pullup resistors to V MAX223 __ High Low __ ActiveCC are built in (except for the MAX220). The pullup resistors force the High High High Impedance outputs of unused drivers low because all drivers invert. Low High Impedance The internal input pullup resistors typically source 12µA, MAX225 __ __ __ High Active except in shutdown mode where the pullups are dis- MAX235 Low Low High Impedance abled. Driver outputs turn off and enter a high-imped- MAX236 Low __ __ High Active ance state—where leakage current is typically MAX240 High X High Impedance microamperes (maximum 25µA)—when in shutdown 14 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers nominal 5kΩ values. The receivers implement Type 1 Shutdown—MAX222–MAX242 interpretation of the fault conditions of V.28 and On the MAX222‚ MAX235‚ MAX236‚ MAX240‚ and EIA/TIA-232E. MAX241‚ all receivers are disabled during shutdown. The receiver input hysteresis is typically 0.5V with a On the MAX223 and MAX242‚ two receivers continue to guaranteed minimum of 0.2V. This produces clear out- operate in a reduced power mode when the chip is in put transitions with slow-moving input signals, even shutdown. Under these conditions‚ the propagation with moderate amounts of noise and ringing. The delay increases to about 2.5µs for a high-to-low input receiver propagation delay is typically 600ns and is transition. When in shutdown, the receiver acts as a independent of input swing direction. CMOS inverter with no hysteresis. The MAX223 and MAX242 also have a receiver output enable input (EN Low-Power Receive Mode for the MAX242 and EN for the MAX223) that allows The low-power receive mode feature of the MAX223, receiver output control independent of SHDN (SHDN MAX242, and MAX245–MAX249 puts the IC into shut- for MAX241). With all other devices‚ SHDN (SHDN for down mode but still allows it to receive information. This MAX241) also disables the receiver outputs. is important for applications where systems are periodi- The MAX225 provides five transmitters and five cally awakened to look for activity. Using low-power receivers‚ while the MAX245 provides ten receivers and receive mode, the system can still receive a signal that eight transmitters. Both devices have separate receiver will activate it on command and prepare it for communi- and transmitter-enable controls. The charge pumps cation at faster data rates. This operation conserves turn off and the devices shut down when a logic high is system power. applied to the ENT input. In this state, the supply cur- Negative Threshold—MAX243 rent drops to less than 25µA and the receivers continue The MAX243 is pin compatible with the MAX232A, differ- to operate in a low-power receive mode. Driver outputs ing only in that RS-232 cable fault protection is removed enter a high-impedance state (three-state mode). On on one of the two receiver inputs. This means that control the MAX225‚ all five receivers are controlled by the lines such as CTS and RTS can either be driven or left ENR input. On the MAX245‚ eight of the receiver out- unconnected without interrupting communication. puts are controlled by the ENR input‚ while the remain- Different cables are not needed to interface with different ing two receivers (RA5 and RB5) are always active. pieces of equipment. RA1–RA4 and RB1–RB4 are put in a three-state mode when ENR is a logic high. The input threshold of the receiver without cable fault protection is -0.8V rather than +1.4V. Its output goes Receiver and Transmitter Enable positive only if the input is connected to a control line Control Inputs that is actively driven negative. If not driven, it defaults The MAX225 and MAX245–MAX249 feature transmitter to the 0 or “OK to send” state. Normally‚ the MAX243’s and receiver enable controls. other receiver (+1.4V threshold) is used for the data line The receivers have three modes of operation: full-speed (TD or RD)‚ while the negative threshold receiver is con- receive (normal active)‚ three-state (disabled)‚ and low- nected to the control line (DTR‚ DTS‚ CTS‚ RTS, etc.). power receive (enabled receivers continue to function Other members of the RS-232 family implement the at lower data rates). The receiver enable inputs control optional cable fault protection as specified by EIA/TIA- the full-speed receive and three-state modes. The 232E specifications. This means a receiver output goes transmitters have two modes of operation: full-speed high whenever its input is driven negative‚ left uncon- transmit (normal active) and three-state (disabled). The nected‚ or shorted to ground. The high output tells the transmitter enable inputs also control the shutdown serial communications IC to stop sending data. To mode. The device enters shutdown mode when all avoid this‚ the control lines must either be driven or transmitters are disabled. Enabled receivers function in connected with jumpers to an appropriate positive volt- the low-power receive mode when in shutdown. age level. Maxim Integrated 15 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers Tables 1a–1d define the control states. The MAX244 The MAX249 provides ten receivers and six drivers with has no control pins and is not included in these tables. four control pins. The ENRA and ENRB receiver enable The MAX246 has ten receivers and eight drivers with inputs each control five receiver outputs. The ENTA two control pins, each controlling one side of the and ENTB transmitter enable inputs control three dri- device. A logic high at the A-side control input (ENA) vers each. There is no always-active receiver. The causes the four A-side receivers and drivers to go into device enters shutdown mode and transmitters go into a three-state mode. Similarly, the B-side control input a three-state mode with a logic high on both ENTA and (ENB) causes the four B-side drivers and receivers to ENTB. In shutdown mode, active receivers operate in a go into a three-state mode. As in the MAX245, one A- low-power receive mode at data rates up to 20kb/s. side and one B-side receiver (RA5 and RB5) remain __________Applications Information active at all times. The entire device is put into shut- down mode when both the A and B sides are disabled Figures 5 through 25 show pin configurations and typi- (ENA = ENB = +5V). cal operating circuits. In applications that are sensitive to power-supply noise, V should be decoupled to The MAX247 provides nine receivers and eight drivers CCground with a capacitor of the same value as C1 and with four control pins. The ENRA and ENRB receiver C2 connected as close as possible to the device. enable inputs each control four receiver outputs. The ENTA and ENTB transmitter enable inputs each control four drivers. The ninth receiver (RB5) is always active. The device enters shutdown mode with a logic high on both ENTA and ENTB. The MAX248 provides eight receivers and eight drivers with four control pins. The ENRA and ENRB receiver enable inputs each control four receiver outputs. The ENTA and ENTB transmitter enable inputs control four drivers each. This part does not have an always-active receiver. The device enters shutdown mode and trans- mitters go into a three-state mode with a logic high on both ENTA and ENTB. 16 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V INPUT C3 TOP VIEW C5 16 + C1+ 1 16 V 1 VCC C1+ CC 2 C1 +5V TO +10V V+ +10V V+ 32 15 GND C1- VOLTAGE DOUBLER 4 C1- 3 14 T1OUT C2+ +10V TO -10V 6 -10V C2 5 V-C2- VOLTAGE INVERTER C4 C2+ 4 MAX220 13 R1IN MAX232 +5V C2- 5 MAX232A 12 R1OUT 400kΩ V- 6 11 T1IN 11 T1IN T1OUT 14 +5V T2OUT 7 10 T2IN TTL/CMOS RS-232 INPUTS 400kΩ OUTPUTS R2IN 8 9 R2OUT 10 T2IN T2OUT 7 DIP/SO 12 R1OUT R1IN 13 CAPACITANCE (μF) TTL/CMOS 5kΩ RS-232 DEVICE C1 C2 C3 C4 C5 OUTPUTS INPUTS MAX220 0.047 0.33 0.33 0.33 0.33 9 R2OUT R2IN 8 MAX232 1.0 1.0 1.0 1.0 1.0 MAX232A 0.1 0.1 0.1 0.1 0.1 5kΩ GND 15 Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit TOP VIEW +5V INPUT C3 ALL CAPACITORS = 0.1μF C5 17 2 VCC C1+ 3 +10V+ C1 +5V TO +10V V+ (N.C.) EN 1 20 SHDN 4 C1- VOLTAGE DOUBLER + 5 (N.C.) EN 1 18 SHDN C1+ 2 19 VCC C2+C2 +10V TO -10V V- 7 -10V 6 C2- V+ VOLTAGE INVERTER C4C1+ 2 17 VCC 3 18 GND V+ 3 16 GND C1- 4 17 T1OUT +5V 400kΩ (EXCEPT MAX220) C1- 4 15 T1OUT C2+ 5 MAX222 16 N.C. MAX242 12 T1IN T1OUT 15 C2+ 5 MAX222 14 R1IN C2- 6 15 R1IN +5V MAX242 TTL/CMOS C2- V- (EXCEPT MAX220) RS-232 6 13 R1OUT 7 14 R1OUT INPUTS 400kΩ OUTPUTS 11 T2IN T2OUT 8 V- 7 12 T1IN T2OUT 8 13 N.C. T2OUT 8 11 T2IN R2IN 9 12 T1IN 13 R1OUT R1IN 14 R2IN 9 10 R2OUT R2OUT 10 11 T2IN TTL/CMOS 5kΩ RS-232 OUTPUTS INPUTS DIP/SO SSOP 10 R2OUT R2IN 9 1 (N.C.) EN 5kΩ ( ) ARE FOR MAX222 ONLY. 18SHDN PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY. GND 16 Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit Maxim Integrated 17 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V TOP VIEW 0.1μF 28 27 +5V VCC VCC 400kΩ + T1IN3 11 ENR V T1OUT1 28 CC +5V ENR 2 27 V 400kΩCC T2IN T1IN 3 26 ENT 4 12+5V T2OUT T2IN 4 25 T3IN 400kΩ R1OUT 5 MAX225 24 T4IN T3IN25 18 R2OUT 6 23 T5IN +5V T3OUT 400kΩ R3OUT 7 22 R4OUT 24 T4INR3IN 178 21 R5OUT +5V T4OUT R2IN 9 20 R5IN 400kΩ T5IN T5OUTR1IN 10 19 R4IN 23 16 T1OUT 11 18 T3OUT 26 ENT 15 T2OUT 12 17 T4OUT T5OUT GND 13 16 T5OUT R1OUT R1IN5 10 GND 14 15 T5OUT 5kΩ SO R2OUT R2IN6 9 5kΩ 7 R3OUT R3IN 8 MAX225 FUNCTIONAL DESCRIPTION 5 RECEIVERS 5kΩ 5 TRANSMITTERS 22 R4OUT R4IN2 CONTROL PINS 19 1 RECEIVER ENABLE (ENR) 5kΩ 1 TRANSMITTER ENABLE (ENT) R5OUT R5IN 21 20 5kΩ 1 ENR 2 PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED. ENR GND GND CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER. 13 14 Figure 7. MAX225 Pin Configuration and Typical Operating Circuit 18 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V INPUT TOP VIEW 1.0μF 11 12 1.0μF C1+ VCC 13 1.0μF 14 +5V TO +10V V+C1- VOLTAGE DOUBLER 15 C2+ +10V TO -10V 17 1.0μF V-16 C2- VOLTAGE INVERTER 1.0μF +5V 400kΩ 7 T1IN T1 T1OUT 2+ T3OUT 1 28 T4OUT +5V T1OUT 2 27 R3IN 400kΩ 6 T2IN T2OUT 3 T2OUT 3 26 R3OUT T2 R2IN 4 25 SHDN (SHDN) +5V TTL/CMOS RS-232 R2OUT 5 24 EN (EN) INPUTS 400kΩ OUTPUTS MAX223 20 T3IN T3OUT 1 T2IN 6 MAX241 23 R4IN* T3 T1IN 7 22 R4OUT* +5V R1OUT 8 21 T4IN 400kΩ 21 T4IN T4 T4OUT 28R1IN 9 20 T3IN GND 10 19 R5OUT* R1IN VCC 11 18 R5IN* 8 R1OUT R1 9 C1+ 12 17 V- 5kΩ V+ 13 16 C2- 5 R2OUT R2INR2 4 C1- 14 15 C2+ 5kΩ Wide SO/ SSOP LOGIC 26 R3OUT R3IN 27 RS-232R3 OUTPUTS INPUTS 5kΩ 22 R4OUT R4IN R4 23 5kΩ 19 R5OUT R5IN R5 18 *R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN. 5kΩ NOTE: PIN LABELS IN ( ) ARE FOR MAX241. 24 EN (EN) SHDN 25 GND (SHDN) 10 Figure 8. MAX223/MAX241 Pin Configuration and Typical Operating Circuit Maxim Integrated 19 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V INPUT TOP VIEW 1.0μF 7 1.0μF 8 C1+ VCC 9 1.0μF 10 C1- +5V TO +10V V+ + VOLTAGE DOUBLER T3OUT 1 20 T4OUT 11 C2+ +10V TO -10V 12 13 T1OUT 2 19 T5IN 1.0μF C2- VOLTAGE INVERTER V- 1.0μF T2OUT 3 18 N.C. +5V 400kΩ T2IN 4 17 SHDN 5 T1IN T1OUT 2 T1 T1IN 5 MAX230 16 T5OUT +5V 400kΩ GND 6 15 T4IN 4 T2IN T2OUTT2 3 VCC 7 14 T3IN +5V C1+ 400kΩ8 13 V- TTL/CMOS 14 T3IN T3OUTT3 1 RS-232 V+ 9 12 C2- INPUTS +5V OUTPUTS 400kΩ C1- 10 11 C2+ 15 T4IN T4OUTT4 20 +5V 400kΩ DIP/SO 19 T5IN T5OUT 16T5 N.C.x 18 17GND SHDN 6 Figure 9. MAX230 Pin Configuration and Typical Operating Circuit +5V INPUT TOP VIEW 1.0μF +7.5V TO +12V 13 (15) 1 14 C1+ VCC V+ (16) 1.0μF 2 +12V TO -12V 3C1- VOLTAGE CONVERTER V- C2 + + +5V 1.0μF C+ 1 14 V+ C+ 1 16 V+ 400kΩ C- 2 13 VCC C- 2 15 VCC (10) (13)8 T1IN T1OUT 11T1 V- 3 12 GND V- 3 14 GND +5V TTL/CMOS T2OUT 4 MAX231 11 T1OUT T2OUT 4 MAX231 13 T1OUT RS-232INPUTS 400kΩ OUTPUTS R2IN 5 10 R1IN R2IN 5 12 R1IN 7 T2IN T2OUT 4T2 R2OUT 6 9 R1OUT R2OUT 6 11 R1OUT (11) 9 R1OUT R1IN 10 (12) T2IN 7 8 T1IN T2IN 7 10 T1IN R1 N.C. 8 9 N.C. TTL/CMOS 5kΩ RS-232 DIP OUTPUTS INPUTS SO 6 R2OUT R2IN 5 R2 5kΩ GND PIN NUMBERS IN ( ) ARE FOR SO PACKAGE. 12 (14) Figure 10. MAX231 Pin Configurations and Typical Operating Circuit 20 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V INPUT 1.0μF TOP VIEW 7 +5V VCC 400kΩ + 2 T1IN T1OUT 5T2IN 1 20 R2OUT +5V T1IN 2 19 R2IN TTL/CMOS INPUTS 400kΩ RS-232 R1OUT OUTPUTS3 18 T2OUT 1 T2IN T2OUT 18 R1IN 4 17 V- 3 R1OUT R1IN 4 T1OUT 5 MAX233 16 C2- MAX233A GND 6 15 C2+ TTL/CMOS 5kΩ RS-232 OUTPUTS V INPUTSCC 7 14 V+ (C1-) (V+) C1+ 20 R2OUT R2IN 198 13 C1- (C1+) GND 9 12 V- (C2+) 8 (13)DO NOT MAKE C1+ 5kΩ 11 (12)C2+ (V-) CS- 10 11 C2+ (C2-) CONNECTIONS TO 13 (14) 15 THESE PINS C1- C2+ 12 (10) 16 INTERNAL -10V V- C2- DIP/SO POWER SUPPLY 17 V- 10 (11)CS- INTERNAL +10V 14 (8) V+ GND GND POWER SUPPLY 6 9 PIN NAMES IN ( ) ARE FOR SO PACKAGE. Figure 11. MAX233/MAX233A Pin Configuration and Typical Operating Circuit +5V INPUT 1.0μF TOP VIEW 6 1.0μF 7 C1+ VCC 8 1.0μF +5V TO +10V V+9 C1- VOLTAGE DOUBLER 10 C2+ +10V TO -10V 12 + 1.0μF 11 VOLTAGE INVERTER V- T1OUT 1 T3OUT C2- 1.0μF16 +5V T2OUT 2 15 T4OUT 400kΩ T2IN 3 14 T4IN 4 T1IN T1OUT 1 T1 T1IN 4 MAX234 13 T3IN +5V GND 5 12 V- 400kΩ VCC 6 11 C2- 3 T2IN T2OUT 2T2 C1+ 7 10 C2+ TTL/CMOS +5V RS-232 INPUTS 8 9 C1- 400kΩ OUTPUTS V+ 13 T3IN T3OUT 16 T3 DIP/SO +5V 400kΩ 14 T4IN T4OUT 15 T4 GND 5 Figure 12. MAX234 Pin Configuration and Typical Operating Circuit Maxim Integrated 21 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V INPUT TOP VIEW 1.0μF 12 VCC +5V 400kΩ 8 T1IN T1 T1OUT 3 +5V 400kΩ 7 T2IN T2OUTT2 4 +5V 400kΩ TTL/CMOS 15 T3IN T3OUT 2 INPUTS T3 RS-232 OUTPUTS + T4OUT 1 24 R3IN +5V 400kΩ T3OUT 2 23 R3OUT 16 T4IN T4OUTT4 1 T1OUT 3 22 T5IN +5V T2OUT 4 21 SHDN 400kΩ R2IN 5 MAX235 20 EN 22 T5IN T5OUT 19 T5 R2OUT 6 19 T5OUT T2IN 7 18 R4IN 9 R1OUT R1IN 10 T1 T1IN 8 17 R4OUT R1OUT 9 16 T4IN 5kΩ R1IN 10 15 T3IN 6 R2OUT R2IN 5R2 GND 11 14 R5OUT 5kΩ VCC 12 13 R5IN TTL/CMOS 23 R3OUT R3IN 24DIP RS-232OUTPUTS R3 INPUTS 5kΩ 17 R4OUT 18R4 R4IN 5kΩ 14 R5OUT R5IN 13R5 5kΩ 20 EN 21 SHDN GND 11 Figure 13. MAX235 Pin Configuration and Typical Operating Circuit 22 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers TOP VIEW +5V INPUT 1.0μF 9 1.0μF 10 11 C1+ VCC V+ 1.0μF +5V TO +10V12 C1- VOLTAGE DOUBLER 13 C2+ 15V- 1.0μF +10V TO -10V14 C2- VOLTAGE INVERTER 1.0μF +5V 400kΩ 7 T1IN T1OUTT1 2 + T3OUT 1 24 T4OUT +5V T1OUT 2 23 R2IN 400kΩ 6 T2IN T2OUT 3 T2OUT 3 22 R2OUT T2 R1IN 4 21 SHDN TTL/CMOS +5V RS-232 INPUTS MAX236 400kΩ OUTPUTSR1OUT 5 20 EN 18 T3IN T3OUT 1 T2IN 6 19 T4IN T3 T1IN 7 18 T3IN +5V 400kΩ GND 8 17 R3OUT 19 T4IN T4OUT 24 VCC 9 16 R3IN T4 C1+ 10 15 V- V+ 11 14 C2- 5 R1OUT R1INR1 4 C1- 12 13 C2+ 5kΩ DIP/SO 22 TTL/CMOS R2OUT R2IN 23R2 RS-232 OUTPUTS INPUTS 5kΩ 17 R3OUT R3IN 16 R3 5kΩ 20 EN 21 SHDN GND 8 Figure 14. MAX236 Pin Configuration and Typical Operating Circuit Maxim Integrated 23 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers TOP VIEW +5V INPUT 1.0μF 9 1.0μF 10 C1+ VCC 11 +5V TO +10V V+ 1.0μF 12 C1- VOLTAGE DOUBLER 13 15C2+ V- 1.0μF +10V TO -10V14 VOLTAGE INVERTER 1.0μFC2- +5V 400kΩ + T3OUT 1 24 T4OUT 7 T1IN T1 T1OUT 2 T1OUT 2 23 R2IN +5V 400kΩ T2OUT 3 22 R2OUT 6 T2IN T2OUT 3 R1IN 4 21 T5IN T2+5V R1OUT 5 MAX237 20 T5OUT 400kΩ T2IN 6 19 T4IN TTL/CMOS 18 T3IN T3OUT 1T3 RS-232 T1IN 7 18 T3IN INPUTS +5V OUTPUTS 400kΩ GND 8 17 R3OUT V 19 T4IN T4OUT 24CC 9 16 R3IN T4 +5V C1+ 10 15 V- 400kΩ V+ 11 14 C2- 21 T5IN T5OUT 20 T5 C1- 12 13 C2+ DIP/SO 5 R1OUT R1 R1IN 4 5kΩ 22 R2OUT R2IN 23 TTL/CMOS R2 RS-232 OUTPUTS INPUTS 5kΩ 17 R3OUT R3IN 16 R3 5kΩ GND 8 Figure 15. MAX237 Pin Configuration and Typical Operating Circuit 24 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers TOP VIEW +5V INPUT 1.0μF 9 1.0μF 10 C1+ VCC V+ 11 μ +5V TO +10V1.0 F 12 C1- VOLTAGE DOUBLER 13 C2+ 15 1.0μF +10V TO -10V V-14 C2- VOLTAGE INVERTER 1.0μF +5V 400kΩ + T2OUT 1 24 T3OUT 5 T1IN T1 T1OUT 2 T1OUT 2 23 R3IN +5V 400kΩ R2IN 3 22 R3OUT 18 T2IN T2OUT 1 R2OUT 4 21 T4IN T2 +5V T1IN 5 MAX238 20 T4OUT TTL/CMOS 400kΩ RS-232INPUTS OUTPUTS R1OUT 6 19 T3IN 19 T3IN T3OUT 24T3 R1IN 7 18 T2IN +5V GND 8 17 R4OUT 400kΩ VCC 9 16 R4IN 21 T4IN T4 T4OUT 20 C1+ 10 15 V- V+ 11 14 C2- C1- 12 13 C2+ 6 R1OUT R1 R1IN 7 DIP/SO 5kΩ 4 R2OUT R2 R2IN 3 TTL/CMOS 5kΩ RS-232 OUTPUTS INPUTS 22 R3OUT R3 R3IN 23 5kΩ 17 R4OUT 16 R4 R4IN 5kΩ GND 8 Figure 16. MAX238 Pin Configuration and Typical Operating Circuit Maxim Integrated 25 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers TOP VIEW +7.5V TO +13.2V +5V INPUT INPUT 1.0μF 4 5 6 VCC V+C1+ 8V- 1.0μF +10V TO -10V7 C1- VOLTAGE INVERTER 1.0μF +5V 400kΩ 24 T1IN T1 T1OUT 19 + R1OUT 1 24 T1IN +5V 400kΩ R1IN 2 23 T2IN TTL/CMOS 23 T2IN T2OUT 20GND 3 22 R2OUT T2 RS-232 INPUTS OUTPUTS V 4 21 R2IN +5VCC 400kΩ V+ 5 MAX239 20 T2OUT 16 T3IN T3OUT 13 C+ 6 19 T1OUT T3 C- 7 18 R3IN V- 8 17 R3OUT 1 R1OUT R1INR1 2 R5IN 9 16 T3IN 5kΩ R5OUT 10 15 N.C. R4OUT 11 14 EN 22 R2OUT R2INR2 21 R4IN 12 13 T3OUT 5kΩ DIP/SO TTL/CMOS 17 R3OUT R3IN 18R3 RS-232 OUTPUTS INPUTS 5kΩ 11 R4OUT R4IN 12 R4 5kΩ 10 R5OUT R5IN R5 9 5kΩ 14 EN 15N.C. GND 3 Figure 17. MAX239 Pin Configuration and Typical Operating Circuit 26 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V INPUT TOP VIEW 1.0μF 19 25 1.0μF C1+ VCC 26 1.0μF 27 +5V TO +10V V+ C1- VOLTAGE DOUBLER 28 C2+ +5V TO -10V 30 1.0μF 29 C2- VOLTAGE INVERTER V- 1.0μF +5V 400kΩ 15 T1IN T1 T1OUT 7 +5V 400kΩ 14 T2IN T2OUTT2 8 +5V 400kΩ TTL/CMOS 37 T3IN T3OUT 6 RS-232T3 INPUTS OUTPUTS +5V + 400kΩ N.C. 12 44 N.C. 38 T4IN T4OUT 5 R2OUT 13 43 SHDN T4 T2IN 14 42 EN +5V 400kΩ T1IN 15 41 T5OUT R1OUT 16 40 R4IN 2 T5IN T5OUTT5 41 R1IN 17 39 R4OUT GND 18 MAX240 38 T4IN 16 R1OUT R1IN R1 17VCC 19 37 T3IN N.C. 20 36 R5OUT 5kΩ N.C. 21 35 R5IN N.C. 22 34 N.C. 13 R2OUT R2INR2 10 5kΩ TTL/CMOS 3 R3OUT R3IN 4 RS-232R3 OUTPUTS INPUTS 5kΩ Plastic FP 39 R4OUT R4IN R4 40 5kΩ 36 R5OUT R5IN R5 35 5kΩ 42 EN SHDN 43 GND 18 Figure 18. MAX240 Pin Configuration and Typical Operating Circuit Maxim Integrated 27 N.C. 23 11 N.C. N.C. 24 10 R2IN C1+ 25 9 N.C. V+ 26 8 T2OUT C1- 27 7 T1OUT C2+ 28 6 T3OUT C2 29 5 T4OUT V- 30 4 R3IN N.C. 31 3 R3OUT N.C. 32 2 T5IN N.C. 33 1 N.C. MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers TOP VIEW +5V INPUT 0.1μF 0.1μF 16 1 C1+ VCC 0.1μF +5V TO +10V 2 V+ +10V 3 C1- VOLTAGE DOUBLER + 4 C2+ C1+ 1 16 VCC +10V TO -10V 6 -10V 0.1μF 5 C2- VOLTAGE INVERTER V- V+ 2 15 GND 0.1μF C1- 3 14 T1OUT +5V C2+ 4 MAX243 13 R1IN 400kΩ C2- 5 12 R1OUT 11 T1IN T1OUT 14 V- 6 11 T1IN +5V TTL/CMOS RS-232 T2OUT 7 10 T2IN INPUTS 400kΩ OUTPUTS R2IN 8 9 R2OUT 10 T2IN T2OUT 7 DIP/SO 12 R1OUT R1IN 13 TTL/CMOS 5kΩ RS-232 OUTPUTS INPUTS 9 R2OUT R2IN 8 RECEIVER INPUT R1 OUTPUT R2 OUTPUT ≤ -3V HIGH HIGH 5kΩ OPEN HIGH LOW ≥ +3V LOW LOW GND 15 Figure 19. MAX243 Pin Configuration and Typical Operating Circuit 28 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V TOP VIEW 1μF 1μF 20 21 C1+ VCC 22 1μF 23 C1- +5V TO +10V VOLTAGE DOUBLER V+ 24 26 C2+ V- 1μF 1μF 6 5 4 3 2 1 44 43 42 41 40 25 C2- +10V TO -10V VOLTAGE INVERTER + 2 TA1OUT +5V +5V TB1OUT 44 400kΩ 15 TA1IN TB1IN 30 RA3IN 7 39 RB4IN RA2IN 8 38 RB3IN 2 TA2OUT +5V +5V TB2OUT 43 RA1IN 9 37 RB2IN 400kΩ RA1OUT 10 36 RB1IN 16 TA2IN TB2IN 29 RA2OUT 11 35 RB1OUT RA3OUT MAX24412 34 RB2OUT 3 TA3OUT +5V +5V TB3OUT 42 RA4OUT 13 33 RB3OUT 400kΩ RA5OUT 14 32 RB4OUT 17 TA3IN TB3IN 28 TA1IN 15 31 RB5OUT 4 TA4OUT +5V +5V TB4OUT 41 TA2IN 16 30 TB1IN 400kΩ TA3IN 17 29 TB2IN 18 TA4IN TB4IN 27 9 RA1IN RB1IN 36 18 19 20 21 22 23 24 25 26 27 28 5kΩ 5kΩ PLCC 10 RA1OUT RB1OUT 35 8 RA2IN RB2IN 37 5kΩ 5kΩ MAX249 FUNCTIONAL DESCRIPTION 10 RECEIVERS 11 RA2OUT RB2OUT 34 5 A-SIDE RECEIVERS 7 RA3IN RB3IN 38 5 B-SIDE RECEIVERS 8 TRANSMITTERS 5kΩ 5kΩ 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS 12 RA3OUT RB3OUT 33 NO CONTROL PINS 6 RA4IN RB4IN 39 5kΩ 5kΩ 13 RA4OUT RB4OUT 32 5 RA5IN RB5IN 40 5kΩ 5kΩ 14 RA5OUT RB5OUT 31 GND 19 Figure 20. MAX244 Pin Configuration and Typical Operating Circuit Maxim Integrated 29 TA4IN RA4IN GND RA5IN VCC TA4OUT C1+ TA3OUT V+ TA2OUT C1- TA1OUT C2+ TB1OUT C2- TB2OUT V- TB3OUT TB4IN TB4OUT TB3IN RB5IN MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V TOP VIEW 1μF 40 + VCC ENR 1 40 VCC 16 TA1OUT +5V +5V TB1OUT 24 400kΩ TA1IN 2 39 ENT 2 TA1IN TB1IN 38 TA2IN 3 38 TB1IN +5V TA3IN 4 37 TB2IN 17 TA2OUT +5V TB2OUT 23 400kΩ TA4IN 5 36 TB3IN 3 TA2IN TB2IN 37 RA5OUT 6 35 TB4IN +5V +5V RA4OUT 7 MAX245 34 RB5OUT 18 TA3OUT TB3OUT 22 400kΩ RA3OUT 8 33 RB4OUT 4 TA3IN TB3IN 36 RA2OUT 9 32 RB3OUT 19 TA4OUT +5V +5V TB4OUT 21 RA1OUT 10 31 RB2OUT 400kΩ RA1IN 11 30 RB1OUT 5 TA4IN TB4IN 35 RA2IN 12 29 RB1IN 1 ENR ENT 39 RA3IN 13 28 RB2IN RA4IN 14 27 RB3IN 11 RA1IN RB1IN 29 RA5IN 15 26 RB4IN 5kΩ 5kΩ TA1OUT 16 25 RB5IN TA2OUT 17 24 TB1OUT 10 RA1OUT RB1OUT 30 12 RA2IN RB2IN 28 TA3OUT 18 23 TB2OUT TA4OUT 19 22 TB3OUT 5kΩ 5kΩ GND 20 21 TB4OUT 9 RA2OUT RB2OUT 31 DIP 13 RA3IN RB3IN 27 5kΩ 5kΩ MAX245 FUNCTIONAL DESCRIPTION 8 RA3OUT RB3OUT 32 10 RECEIVERS 14 RA4IN RB4IN 26 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 5kΩ 5kΩ 8 TRANSMITTTERS 7 RA4OUT RB4OUT 33 4 A-SIDE TRANSMITTERS 15 RA5IN RB5IN 25 2 CONTROL PINS 1 RECEIVER ENABLE (ENR) 5kΩ 5kΩ 1 TRANSMITTER ENABLE (ENT) 6 RA5OUT RB5OUT 34 GND 20 Figure 21. MAX245 Pin Configuration and Typical Operating Circuit 30 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V TOP VIEW 1μF 40 + ENA 1 40 V VCCCC +5V +5V TA1IN 2 39 ENB 16 TA1OUT TB1OUT 24 400kΩ TA2IN 3 38 TB1IN 2 TA1IN TB1IN 38 TA3IN 4 37 TB2IN +5V +5V TA4IN 5 36 TB3IN 17 TA2OUT TB2OUT 23 400kΩ RA5OUT 6 35 TB4IN 3 TA2IN TB2IN 37 RA4OUT 7 MAX246 34 RB5OUT +5V +5V RA3OUT 8 33 RB4OUT 18 TA3OUT TB3OUT 22 RA2OUT 9 32 RB3OUT 400kΩ 4 TA3IN TB3IN 36 RA1OUT 10 31 RB2OUT +5V +5V RA1IN 11 30 RB1OUT 19 TA4OUT TB4OUT 21 RA2IN 12 29 RB1IN 400kΩ 5 TA4IN TB4IN 35 RA3IN 13 28 RB2IN 1 ENA ENB 39 RA4IN 14 27 RB3IN 11 RA1IN RB1IN 29 RA5IN 15 26 RB4IN TA1OUT 16 25 RB5IN 5kΩ 5kΩ TA2OUT 17 24 TB1OUT 10 RA1OUT RB1OUT 30 TA3OUT 18 23 TB2OUT 12 RA2IN RB2IN 28 TA4OUT 19 22 TB3OUT GND 20 21 TB4OUT 5kΩ 5kΩ DIP 9 RA2OUT RB2OUT 31 13 RA3IN RB3IN 27 MAX246 FUNCTIONAL DESCRIPTION 5kΩ 5kΩ 10 RECEIVERS 8 RA3OUT RB3OUT 32 5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE) 14 RA4IN RB4IN 26 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 8 TRANSMITTERS 5kΩ 5kΩ 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS 7 RA4OUT RB4OUT 33 2 CONTROL PINS 15 RA5IN RB5IN 25 ENABLE A-SIDE (ENA) ENABLE B-SIDE (ENB) 5kΩ 5kΩ 6 RA5OUT GND RB5OUT 34 20 Figure 22. MAX246 Pin Configuration and Typical Operating Circuit Maxim Integrated 31 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V TOP VIEW 1μF 40 + 1 ENTA VCC ENTB 39 ENTA 1 40 VCC +5V +5V 16 TA1OUT TB1OUT 24 TA1IN 2 39 ENTB 400kΩ TA2IN 3 38 TB1IN 2 TA1IN TB1IN 38 TA3IN 4 37 TB2IN +5V +5V 17 TA2OUT TB2OUT 23 TA4IN 5 36 TB3IN 400kΩ RB5OUT 6 35 TB4IN 3 TA2IN TB2IN 37 RA4OUT 7 MAX247 34 RB4OUT +5V +5V RB3OUT 18 TA3OUT TB3OUT 22RA3OUT 8 33 400kΩ RA2OUT 9 32 RB2OUT 4 TA3IN TB3IN 36 RA1OUT 10 31 RB1OUT +5V +5V ENRA 11 30 ENRB 19 TA4OUT TB4OUT 21 400kΩ RA1IN 12 29 RB1IN 5 TA4IN TB4IN 35 RA2IN 13 28 RB2IN 6 RB5OUT RB5IN 25 RA3IN 14 27 RB3IN RA4IN 15 26 RB4IN 5kΩ TA1OUT 16 25 RB5IN TA2OUT 17 24 TB1OUT 12 RA1IN RB1IN 29 TA3OUT 18 23 TB2OUT 5kΩ 5kΩ TA4OUT 19 22 TB3OUT GND 20 21 TB4OUT 10 RA1OUT RB1OUT 31 13 RA2IN RB2IN 28 DIP 5kΩ 5kΩ MAX247 FUNCTIONAL DESCRIPTION 9 RECEIVERS 9 RA2OUT RB2OUT 32 4 A-SIDE RECEIVERS 14 RA3IN RB3IN 27 5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 8 TRANSMITTERS 5kΩ 5kΩ 4 A-SIDE TRANSMITTERS 4 B-SIDE TRANSMITTERS 8 RA3OUT RB3OUT 33 4 CONTROL PINS 15 RA4IN RB4IN 26 ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) 5kΩ 5kΩ ENABLE RECEIVER A-SIDE (ENTA) 7 RA4OUT RB4OUT 34 ENABLE RECEIVER B-SIDE (ENTB) 11 ENRA ENRB 30 GND 20 Figure 23. MAX247 Pin Configuration and Typical Operating Circuit 32 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers TOP VIEW +5V 1μF 1μF 20 21 C1+ VCC 22 1μF 23 V+C1- +5V TO +10V VOLTAGE DOUBLER 26 24 C2+ V- 1μF 6 5 4 3 2 1 44 43 42 41 40 1μF 25 C2- +10V TO -10V VOLTAGE INVERTER + 18 ENTA ENTB 27+5V +5V 1 TA1OUT TB1OUT 44 RA2IN 7 39 RB3IN 400kΩ RA1IN 8 38 RB2IN 14 TA1IN TB1IN 31 ENRA 9 37 RB1IN +5V +5V RA1OUT 10 36 ENRB 2 TA2OUT TB2OUT 43 RA2OUT 11 35 RB1OUT 400kΩ RA3OUT MAX24812 34 RB2OUT 15 TA2IN TB2IN 30 RA4OUT 13 33 RB3OUT +5V +5V TA1IN 14 32 RB4OUT 3 TA3OUT TB3OUT 42 TA2IN 15 31 TB1IN 400kΩ 16 TA3IN TB3IN 29 TA3IN 16 30 TB2IN TA4IN 17 29 TB3IN +5V +5V 4 TA4OUT TB4OUT 41 19 21 22 23 24 25 26 27 400kΩ18 20 28 17 TA4IN TB4IN 28 PLCC 8 RA1IN RB1IN 37 5kΩ 5kΩ MAX248 FUNCTIONAL DESCRIPTION 10 RA1OUT RB1OUT 35 8 RECEIVERS 7 RA2IN RB2IN 38 4 A-SIDE RECEIVERS 4 B-SIDE RECEIVERS 5kΩ 5kΩ 8 TRANSMITTERS 4 A-SIDE TRANSMITTERS 11 RA2OUT RB2OUT 34 4 B-SIDE TRANSMITTERS 6 RA3IN RB3IN 39 4 CONTROL PINS ENABLE RECEIVER A-SIDE (ENRA) 5kΩ 5kΩ ENABLE RECEIVER B-SIDE (ENRB) 12 RA3OUT RB3OUT 33 ENABLE RECEIVER A-SIDE (ENTA) 5 RA4IN RB4IN 40 ENABLE RECEIVER B-SIDE (ENTB) 5kΩ 5kΩ 13 RA4OUT RB4OUT 32 9 ENRA ENRB 36 GND 19 Figure 24. MAX248 Pin Configuration and Typical Operating Circuit Maxim Integrated 33 ENTA RA3IN GND RA4IN VCC TA4OUT C1+ TA3OUT V+ TA2OUT C1- TA1OUT C2+ TB1OUT C2- TB2OUT V- TB3OUT ENTB TA4OUT TB4IN RB4IN MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers +5V TOP VIEW 1μF 1μF 20 21 C1+ VCC 22 1μF 23 V+C1- +5V TO +10V VOLTAGE DOUBLER 26 24 C2+ V- 1μF 6 5 4 3 2 1 44 43 42 41 40 1μF 25 C2- +10V TO -10V VOLTAGE INVERTER + 18 ENTA ENTB 27 +5V +5V 1 TA1OUT TB1OUT 44 RA2IN 7 39 RB3IN 400kΩ RA1IN 8 38 RB2IN 15 TA1IN TB1IN 30 ENRA 9 37 RB1IN +5V +5V RA1OUT 10 36 ENRB 2 TA2OUT TB2OUT 43 RA2OUT 11 35 RB1OUT 400kΩ RA3OUT MAX24912 34 RB2OUT 16 TA2IN TB2IN 29 RA4OUT 13 33 RB3OUT +5V +5V RA5OUT 14 32 RB4OUT 3 TA3OUT TB3OUT 42 TA1IN 15 31 RB5OUT 400kΩ 17 TA3IN TB3IN 28 TA2IN 16 30 TB1IN TA3IN 17 29 TB2IN 8 RA1IN RB1IN 37 18 19 20 21 22 23 24 25 26 27 28 5kΩ 5kΩ 10 RA1OUT RB1OUT 35 PLCC 7 RA2IN RB2IN 38 5kΩ 5kΩ MAX249 FUNCTIONAL DESCRIPTION 11 RA2OUT RB2OUT 34 10 RECEIVERS 6 RA3IN RB3IN 39 5 A-SIDE RECEIVERS 5 B-SIDE RECEIVERS 5kΩ 5kΩ 6 TRANSMITTERS 12 RA3OUT RB3OUT 33 3 A-SIDE TRANSMITTERS 5 RA4IN RB4IN 40 3 B-SIDE TRANSMITTERS 4 CONTROL PINS 5kΩ 5kΩ ENABLE RECEIVER A-SIDE (ENRA) ENABLE RECEIVER B-SIDE (ENRB) 13 RA4OUT RB4OUT 32 ENABLE RECEIVER A-SIDE (ENTA) 4 RA5IN RB5IN 41 ENABLE RECEIVER B-SIDE (ENTB) 5kΩ 5kΩ 14 RA5OUT RB5OUT 31 9 ENRA ENRB 36 GND 19 Figure 25. MAX249 Pin Configuration and Typical Operating Circuit 34 Maxim Integrated ENTA RA3IN GND RA4IN VCC RA5IN C1+ TA3OUT V+ TA2OUT C1- TA1OUT C2+ TB1OUT C2- TB2OUT V- TB3OUT ENTB RB5IN TB3IN RB4IN MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ___________________________________________Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE PART TEMP RANGE PIN-PACKAGE MAX222CPN+ 0°C to +70°C 18 Plastic DIP MAX232AC/D 0°C to +70°C Dice* MAX222CWN+ 0°C to +70°C 18 Wide SO MAX232AEPE+ -40°C to +85°C 16 Plastic DIP MAX222C/D 0°C to +70°C Dice* MAX232AESE+ -40°C to +85°C 16 Narrow SO MAX222EPN+ -40°C to +85°C 18 Plastic DIP MAX232AEWE+ -40°C to +85°C 16 Wide SO MAX222EWN+ -40°C to +85°C 18 Wide SO MAX232AEJE -40°C to +85°C 16 CERDIP MAX222EJN -40°C to +85°C 18 CERDIP MAX232AMJE -55°C to +125°C 16 CERDIP MAX222MJN -55°C to +125°C 18 CERDIP MAX232AMLP+ -55°C to +125°C 20 LCC MAX223CAI+ 0°C to +70°C 28 SSOP MAX233CPP+ 0°C to +70°C 20 Plastic DIP MAX223CWI+ 0°C to +70°C 28 Wide SO MAX233EPP+ -40°C to +85°C 20 Plastic DIP MAX223C/D 0°C to +70°C Dice* MAX233ACPP+ 0°C to +70°C 20 Plastic DIP MAX223EAI+ -40°C to +85°C 28 SSOP MAX233ACWP+ 0°C to +70°C 20 Wide SO MAX223EWI+ -40°C to +85°C 28 Wide SO MAX233AEPP+ -40°C to +85°C 20 Plastic DIP MAX225CWI+ 0°C to +70°C 28 Wide SO MAX233AEWP+ -40°C to +85°C 20 Wide SO MAX225EWI+ -40°C to +85°C 28 Wide SO MAX234CPE+ 0°C to +70°C 16 Plastic DIP MAX230CPP+ 0°C to +70°C 20 Plastic DIP MAX234CWE+ 0°C to +70°C 16 Wide SO MAX230CWP+ 0°C to +70°C 20 Wide SO MAX234C/D 0°C to +70°C Dice* MAX230C/D 0°C to +70°C Dice* MAX234EPE+ -40°C to +85°C 16 Plastic DIP MAX230EPP+ -40°C to +85°C 20 Plastic DIP MAX234EWE+ -40°C to +85°C 16 Wide SO MAX230EWP+ -40°C to +85°C 20 Wide SO MAX234EJE -40°C to +85°C 16 CERDIP MAX230EJP -40°C to +85°C 20 CERDIP MAX234MJE -55°C to +125°C 16 CERDIP MAX230MJP -55°C to +125°C 20 CERDIP MAX235CPG+ 0°C to +70°C 24 Wide Plastic DIP MAX231CPD+ 0°C to +70°C 14 Plastic DIP MAX235EPG+ -40°C to +85°C 24 Wide Plastic DIP MAX231CWE+ 0°C to +70°C 16 Wide SO MAX235EDG -40°C to +85°C 24 Ceramic SB MAX231CJD 0°C to +70°C 14 CERDIP MAX235MDG -55°C to +125°C 24 Ceramic SB MAX231C/D 0°C to +70°C Dice* MAX236CNG+ 0°C to +70°C 24 Narrow Plastic DIP MAX231EPD+ -40°C to +85°C 14 Plastic DIP MAX236CWG+ 0°C to +70°C 24 Wide SO MAX231EWE+ -40°C to +85°C 16 Wide SO MAX236C/D 0°C to +70°C Dice* MAX231EJD -40°C to +85°C 14 CERDIP MAX236ENG+ -40°C to +85°C 24 Narrow Plastic DIP MAX231MJD -55°C to +125°C 14 CERDIP MAX236EWG+ -40°C to +85°C 24 Wide SO MAX232CPE+ 0°C to +70°C 16 Plastic DIP MAX236ERG -40°C to +85°C 24 Narrow CERDIP MAX232CSE+ 0°C to +70°C 16 Narrow SO MAX236MRG -55°C to +125°C 24 Narrow CERDIP MAX232CWE+ 0°C to +70°C 16 Wide SO MAX237CNG+ 0°C to +70°C 24 Narrow Plastic DIP MAX232C/D 0°C to +70°C Dice* MAX237CWG+ 0°C to +70°C 24 Wide SO MAX232EPE+ -40°C to +85°C 16 Plastic DIP MAX237C/D 0°C to +70°C Dice* MAX232ESE+ -40°C to +85°C 16 Narrow SO MAX237ENG+ -40°C to +85°C 24 Narrow Plastic DIP MAX232EWE+ -40°C to +85°C 16 Wide SO MAX237EWG+ -40°C to +85°C 24 Wide SO MAX232EJE -40°C to +85°C 16 CERDIP MAX237ERG -40°C to +85°C 24 Narrow CERDIP MAX232MJE -55°C to +125°C 16 CERDIP MAX237MRG -55°C to +125°C 24 Narrow CERDIP MAX232MLP+ -55°C to +125°C 20 LCC MAX238CNG+ 0°C to +70°C 24 Narrow Plastic DIP MAX232ACPE+ 0°C to +70°C 16 Plastic DIP MAX238CWG+ 0°C to +70°C 24 Wide SO MAX232ACSE+ 0°C to +70°C 16 Narrow SO MAX238C/D 0°C to +70°C Dice* MAX232ACWE+ 0°C to +70°C 16 Wide SO +Denotes a lead(Pb)-free/RoHS-compliant package. *Contact factory for dice specifications. Maxim Integrated 35 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers ___________________________________________Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE PART TEMP RANGE PIN-PACKAGE MAX238ENG+ -40°C to +85°C 24 Narrow Plastic DIP MAX243CPE+ 0°C to +70°C 16 Plastic DIP MAX238EWG+ -40°C to +85°C 24 Wide SO MAX243CSE+ 0°C to +70°C 16 Narrow SO MAX238ERG -40°C to +85°C 24 Narrow CERDIP MAX243CWE+ 0°C to +70°C 16 Wide SO MAX238MRG -55°C to +125°C 24 Narrow CERDIP MAX243C/D 0°C to +70°C Dice* MAX239CNG+ 0°C to +70°C 24 Narrow Plastic DIP MAX243EPE+ -40°C to +85°C 16 Plastic DIP MAX239CWG+ 0°C to +70°C 24 Wide SO MAX243ESE+ -40°C to +85°C 16 Narrow SO MAX239C/D 0°C to +70°C Dice* MAX243EWE+ -40°C to +85°C 16 Wide SO MAX239ENG+ -40°C to +85°C 24 Narrow Plastic DIP MAX243EJE -40°C to +85°C 16 CERDIP MAX239EWG+ -40°C to +85°C 24 Wide SO MAX243MJE -55°C to +125°C 16 CERDIP MAX239ERG -40°C to +85°C 24 Narrow CERDIP MAX244CQH+ 0°C to +70°C 44 PLCC MAX239MRG -55°C to +125°C 24 Narrow CERDIP MAX244C/D 0°C to +70°C Dice* MAX240CMH+ 0°C to +70°C 44 Plastic FP MAX244EQH+ -40°C to +85°C 44 PLCC MAX240C/D 0°C to +70°C Dice* MAX245CPL+ 0°C to +70°C 40 Plastic DIP MAX241CAI+ 0°C to +70°C 28 SSOP MAX245C/D 0°C to +70°C Dice* MAX241CWI+ 0°C to +70°C 28 Wide SO MAX245EPL+ -40°C to +85°C 40 Plastic DIP MAX241C/D 0°C to +70°C Dice* MAX246CPL+ 0°C to +70°C 40 Plastic DIP MAX241EAI+ -40°C to +85°C 28 SSOP MAX246C/D 0°C to +70°C Dice* MAX241EWI+ -40°C to +85°C 28 Wide SO MAX246EPL+ -40°C to +85°C 40 Plastic DIP MAX242CAP+ 0°C to +70°C 20 SSOP MAX247CPL+ 0°C to +70°C 40 Plastic DIP MAX242CPN+ 0°C to +70°C 18 Plastic DIP MAX247C/D 0°C to +70°C Dice* MAX242CWN+ 0°C to +70°C 18 Wide SO MAX247EPL+ -40°C to +85°C 40 Plastic DIP MAX242C/D 0°C to +70°C Dice* MAX248CQH+ 0°C to +70°C 44 PLCC MAX242EPN+ -40°C to +85°C 18 Plastic DIP MAX248C/D 0°C to +70°C Dice* MAX242EWN+ -40°C to +85°C 18 Wide SO MAX248EQH+ -40°C to +85°C 44 PLCC MAX242EJN -40°C to +85°C 18 CERDIP MAX249CQH+ 0°C to +70°C 44 PLCC MAX242MJN -55°C to +125°C 18 CERDIP MAX249EQH+ -40°C to +85°C 44 PLCC +Denotes a lead(Pb)-free/RoHS-compliant package. *Contact factory for dice specifications. 36 Maxim Integrated MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 14 PDIP P14+3 16 PDIP P16+1 16 PDIP P16+2 16 PDIP P16+3 21-0043 18 PDIP P18+5 20 PDIP P20+3 20 PDIP P20M+1 24 PDIP N24+3 24 PDIP P24M+1 — 28 PDIP P28+2 21-0044 40 PDIP P40+1 40 PDIP P40M+2 14 CERDIP J14-3 16 CERDIP J16-3 18 CERDIP J18-2 21-0045 20 CERDIP J20-2 24 CERDIP R24-4 16 SO(N) S16+3 21-0041 90-0097 16 SO(N) S16+5 16 SO(W) W16+1 16 SO(W) W16+2 90-0107 16 SO(W) W16+3 18 SO(W) W18+1 90-0181 20 SO(W) W20+3 21-0042 90-0108 20 SO(W) W20M+1 24 SO(W) W24+2 90-0182 28 SO(W) W28+1 28 SO(W) W28+2 90-0109 28 SO(W) W28M+1 20 LCC L20+3 21-0658 90-0177 20 SSOP A20+1 90-0094 24 SSOP A24+2 90-0110 21-0056 28 SSOP A28+1 90-0095 16 TSSOP U16+1 90-0117 16 FPCK F16-3 21-0013 — 44 MQFP M44+5 21-0826 90-0169 44 PLCC Q44+1 21-0049 90-0236 44 PLCC Q44+2 Maxim Integrated 37 MAX220–MAX249 +5V-Powered, Multichannel RS-232 Drivers/Receivers Revision History REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED Added part information to the lead temperature in the Absolute Maximum Ratings 15 1/06 2, 5, 8 sections Changed multiple packages to lead-free versions; updated/added notes 3, 4, 5, 7, 16 7/10 and 8 to the Electrical Characteristics table; removed incorrect subscripting from all 1, 2–9, 17–36 pin names in the Electrical Characteristics table and Pin Configurations 19-0122; Rev 8; 10/03 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers General Description __Next Generation Device Features The MAX481, MAX483, MAX485, MAX487–MAX491, and ♦ For Fault-Tolerant Applications MAX1487 are low-power transceivers for RS-485 and RS- MAX3430: ±80V Fault-Protected, Fail-Safe, 1/4 422 communication. Each part contains one driver and one receiver. The MAX483, MAX487, MAX488, and MAX489 Unit Load, +3.3V, RS-485 Transceiver feature reduced slew-rate drivers that minimize EMI and MAX3440E–MAX3444E: ±15kV ESD-Protected, reduce reflections caused by improperly terminated cables, ±60V Fault-Protected, 10Mbps, Fail-Safe, thus allowing error-free data transmission up to 250kbps. RS-485/J1708 Transceivers The driver slew rates of the MAX481, MAX485, MAX490, ♦ For Space-Constrained Applications MAX491, and MAX1487 are not limited, allowing them to transmit up to 2.5Mbps. MAX3460–MAX3464: +5V, Fail-Safe, 20Mbps, Profibus RS-485/RS-422 Transceivers These transceivers draw between 120µA and 500µA of supply current when unloaded or fully loaded with disabled MAX3362: +3.3V, High-Speed, RS-485/RS-422 drivers. Additionally, the MAX481, MAX483, and MAX487 Transceiver in a SOT23 Package have a low-current shutdown mode in which they consume MAX3280E–MAX3284E: ±15kV ESD-Protected, only 0.1µA. All parts operate from a single 5V supply. 52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422, Drivers are short-circuit current limited and are protected True Fail-Safe Receivers against excessive power dissipation by thermal shutdown MAX3293/MAX3294/MAX3295: 20Mbps, +3.3V, circuitry that places the driver outputs into a high-imped- SOT23, RS-855/RS-422 Transmitters ance state. The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit. ♦ For Multiple Transceiver Applications MAX3030E–MAX3033E: ±15kV ESD-Protected, The MAX487 and MAX1487 feature quarter-unit-load receiver input impedance, allowing up to 128 MAX487/ +3.3V, Quad RS-422 Transmitters MAX1487 transceivers on the bus. Full-duplex communi- ♦ For Fail-Safe Applications cations are obtained using the MAX488–MAX491, while MAX3080–MAX3089: Fail-Safe, High-Speed the MAX481, MAX483, MAX485, MAX487, and MAX1487 (10Mbps), Slew-Rate-Limited RS-485/RS-422 are designed for half-duplex applications. Transceivers ________________________Applications ♦ For Low-Voltage Applications Low-Power RS-485 Transceivers MAX3483E/MAX3485E/MAX3486E/MAX3488E/ MAX3490E/MAX3491E: +3.3V Powered, ±15kV Low-Power RS-422 Transceivers ESD-Protected, 12Mbps, Slew-Rate-Limited, Level Translators True RS-485/RS-422 Transceivers Transceivers for EMI-Sensitive Applications Industrial-Control Local Area Networks Ordering Information appears at end of data sheet. ______________________________________________________________Selection Table RECEIVER/ QUIESCENT NUMBER OF PART HALF/FULL DATA RATE SLEW-RATE LOW-POWER DRIVER CURRENT TRANSMITTERS PIN NUMBER DUPLEX (Mbps) LIMITED SHUTDOWN ENABLE (µA) ON BUS COUNT MAX481 Half 2.5 No Yes Yes 300 32 8 MAX483 Half 0.25 Yes Yes Yes 120 32 8 MAX485 Half 2.5 No No Yes 300 32 8 MAX487 Half 0.25 Yes Yes Yes 120 128 8 MAX488 Full 0.25 Yes No No 120 32 8 MAX489 Full 0.25 Yes No Yes 120 32 14 MAX490 Full 2.5 No No No 300 32 8 MAX491 Full 2.5 No No Yes 300 32 14 MAX1487 Half 2.5 No No Yes 230 128 8 ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC).............................................................12V 14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW Control Input Voltage (RE, DE)...................-0.5V to (VCC + 0.5V) 8-Pin µMAX (derate 4.1mW/°C above +70°C) ..............830mW Driver Input Voltage (DI).............................-0.5V to (VCC + 0.5V) 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW Driver Output Voltage (A, B)...................................-8V to +12.5V 14-Pin CERDIP (derate 9.09mW/°C above +70°C).......727mW Receiver Input Voltage (A, B).................................-8V to +12.5V Operating Temperature Ranges Receiver Output Voltage (RO).....................-0.5V to (VCC +0.5V) MAX4_ _C_ _/MAX1487C_ A ...............................0°C to +70°C Continuous Power Dissipation (TA = +70°C) MAX4_ _E_ _/MAX1487E_ A.............................-40°C to +85°C 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ....727mW MAX4_ _MJ_/MAX1487MJA ...........................-55°C to +125°C 14-Pin Plastic DIP (derate 10.00mW/°C above +70°C) ..800mW Storage Temperature Range .............................-65°C to +160°C 8-Pin SO (derate 5.88mW/°C above +70°C).................471mW Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Driver Output (no load) VOD1 5 V Differential Driver Output R = 50Ω (RS-422) 2 V V (with load) OD2 R = 27Ω (RS-485), Figure 4 1.5 5 Change in Magnitude of Driver Differential Output Voltage for ∆VOD R = 27Ω or 50Ω, Figure 4 0.2 V Complementary Output States Driver Common-Mode Output V R = 27Ω or 50Ω, Figure 4 3 V Voltage OC Change in Magnitude of Driver Common-Mode Output Voltage ∆VOD R = 27Ω or 50Ω, Figure 4 0.2 V for Complementary Output States Input High Voltage VIH DE, DI, RE 2.0 V Input Low Voltage VIL DE, DI, RE 0.8 V Input Current IIN1 DE, DI, RE ±2 µA DE = 0V; V = 12V 1.0 VCC = 0V or 5.25V, IN mA Input Current all devices except IIN2 MAX487/MAX1487 VIN = -7V -0.8(A, B) MAX487/MAX1487, VIN = 12V 0.25 DE = 0V, VCC = 0V or 5.25V mA VIN = -7V -0.2 Receiver Differential Threshold V -7V ≤ V ≤ 12V -0.2 0.2 V Voltage TH CM Receiver Input Hysteresis ∆VTH VCM = 0V 70 mV Receiver Output High Voltage VOH IO = -4mA, VID = 200mV 3.5 V Receiver Output Low Voltage VOL IO = 4mA, VID = -200mV 0.4 V Three-State (high impedance) IOZR 0.4V ≤ VO ≤ 2.4V ±1 µAOutput Current at Receiver -7V ≤ VCM ≤ 12V, all devices except 12 kΩ MAX487/MAX1487 Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V, MAX487/MAX1487 48 kΩ 2 _______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MAX488/MAX489, 120 250 DE, DI, RE = 0V or VCC MAX490/MAX491, 300 500 DE, DI, RE = 0V or VCC MAX481/MAX485, DE = VCC 500 900 No-Load Supply Current ICC RE = 0V or V µA(Note 3) CC DE = 0V 300 500 MAX1487, DE = VCC 300 500 RE = 0V or VCC DE = 0V 230 400 MAX483 350 650 MAX483/MAX487, DE = 5V RE = 0V or V MAX487 250 400CC DE = 0V 120 250 Supply Current in Shutdown ISHDN MAX481/483/487, DE = 0V, RE = VCC 0.1 10 µA Driver Short-Circuit Current, I -7V ≤ V ≤12V (Note 4) 35 250 mA VO = High OSD1 O Driver Short-Circuit Current, I V = Low OSD2 -7V ≤ VO ≤12V (Note 4) 35 250 mA O Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC 7 95 mA SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487 (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS tPLH Figures 6 and 8, R = 54Ω, 10 30 60 Driver Input to Output DIFF ns tPHL CL1 = CL2 = 100pF 10 30 60 Driver Output Skew to Output tSKEW Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF 5 10 ns Figures 6 and 8, MAX481, MAX485, MAX1487 3 15 40 Driver Rise or Fall Time tR, tF RDIFF = 54Ω, MAX490C/E, MAX491C/E 5 15 25 ns CL1 = CL2 = 100pF MAX490M, MAX491M 3 15 40 Driver Enable to Output High tZH Figures 7 and 9, CL = 100pF, S2 closed 40 70 ns Driver Enable to Output Low tZL Figures 7 and 9, CL = 100pF, S1 closed 40 70 ns Driver Disable Time from Low tLZ Figures 7 and 9, CL = 15pF, S1 closed 40 70 ns Driver Disable Time from High tHZ Figures 7 and 9, CL = 15pF, S2 closed 40 70 ns Figures 6 and 10, MAX481, MAX485, MAX1487 20 90 200 Receiver Input to Output tPLH, tPHL RDIFF = 54Ω, MAX490C/E, MAX491C/E 20 90 150 ns CL1 = CL2 = 100pF MAX490M, MAX491M 20 90 200 | tPLH - tPHL | Differential Figures 6 and 10, RDIFF = 54Ω,tSKD 13 ns Receiver Skew CL1 = CL2 = 100pF Receiver Enable to Output Low tZL Figures 5 and 11, CRL = 15pF, S1 closed 20 50 ns Receiver Enable to Output High tZH Figures 5 and 11, CRL = 15pF, S2 closed 20 50 ns Receiver Disable Time from Low tLZ Figures 5 and 11, CRL = 15pF, S1 closed 20 50 ns Receiver Disable Time from High tHZ Figures 5 and 11, CRL = 15pF, S2 closed 20 50 ns Maximum Data Rate fMAX 2.5 Mbps Time to Shutdown tSHDN MAX481 (Note 5) 50 200 600 ns _______________________________________________________________________________________ 3 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487 (continued) (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Driver Enable from Shutdown to t Figures 7 and 9, C = 100pF, S2 closed 40 100 ns Output High (MAX481) ZH(SHDN) L Driver Enable from Shutdown to t Figures 7 and 9, C = 100pF, S1 closed 40 100 ns Output Low (MAX481) ZL(SHDN) L Receiver Enable from Shutdown Figures 5 and 11, CL = 15pF, S2 closed,t 300 1000 ns to Output High (MAX481) ZH(SHDN) A - B = 2V Receiver Enable from Shutdown Figures 5 and 11, CL = 15pF, S1 closed,tZL(SHDN) 300 1000 nsto Output Low (MAX481) B - A = 2V SWITCHING CHARACTERISTICS—MAX483, MAX487/MAX488/MAX489 (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS tPLH Figures 6 and 8, R = 54Ω, 250 800 2000 Driver Input to Output DIFF ns tPHL CL1 = CL2 = 100pF 250 800 2000 Figures 6 and 8, R = 54Ω, Driver Output Skew to Output t DIFFSKEW 100 800 nsCL1 = CL2 = 100pF Figures 6 and 8, RDIFF = 54Ω,Driver Rise or Fall Time tR, tF 250 2000 nsCL1 = CL2 = 100pF Driver Enable to Output High tZH Figures 7 and 9, CL = 100pF, S2 closed 250 2000 ns Driver Enable to Output Low tZL Figures 7 and 9, CL = 100pF, S1 closed 250 2000 ns Driver Disable Time from Low tLZ Figures 7 and 9, CL = 15pF, S1 closed 300 3000 ns Driver Disable Time from High tHZ Figures 7 and 9, CL = 15pF, S2 closed 300 3000 ns tPLH Figures 6 and 10, R = 54Ω, 250 2000 Receiver Input to Output DIFF ns tPHL CL1 = CL2 = 100pF 250 2000 I tPLH - tPHL I Differential Figures 6 and 10, RDIFF = 54Ω,tSKD 100 ns Receiver Skew CL1 = CL2 = 100pF Receiver Enable to Output Low tZL Figures 5 and 11, CRL = 15pF, S1 closed 20 50 ns Receiver Enable to Output High tZH Figures 5 and 11, CRL = 15pF, S2 closed 20 50 ns Receiver Disable Time from Low tLZ Figures 5 and 11, CRL = 15pF, S1 closed 20 50 ns Receiver Disable Time from High tHZ Figures 5 and 11, CRL = 15pF, S2 closed 20 50 ns Maximum Data Rate fMAX tPLH, tPHL < 50% of data period 250 kbps Time to Shutdown tSHDN MAX483/MAX487 (Note 5) 50 200 600 ns Driver Enable from Shutdown to MAX483/MAX487, Figures 7 and 9, tZH(SHDN) 2000 nsOutput High CL = 100pF, S2 closed Driver Enable from Shutdown to MAX483/MAX487, Figures 7 and 9, tZL(SHDN) 2000 nsOutput Low CL = 100pF, S1 closed Receiver Enable from Shutdown MAX483/MAX487, Figures 5 and 11, t to Output High ZH(SHDN) 2500 ns CL = 15pF, S2 closed Receiver Enable from Shutdown MAX483/MAX487, Figures 5 and 11, tZL(SHDN) 2500 nsto Output Low CL = 15pF, S1 closed 4 _______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers NOTES FOR ELECTRICAL/SWITCHING CHARACTERISTICS Note 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 2: All typical specifications are given for VCC = 5V and TA = +25°C. Note 3: Supply current specification is valid for loaded transmitters when DE = 0V. Note 4: Applies to peak current. See Typical Operating Characteristics. Note 5: The MAX481/MAX483/MAX487 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See Low-Power Shutdown Mode section. __________________________________________Typical Operating Characteristics (VCC = 5V, TA = +25°C, unless otherwise noted.) OUTPUT CURRENT vs. OUTPUT CURRENT vs. RECEIVER OUTPUT HIGH VOLTAGE vs. RECEIVER OUTPUT LOW VOLTAGE RECEIVER OUTPUT HIGH VOLTAGE TEMPERATURE 45 -20 4.8 40 -18 4.6 IRO = 8mA 35 -16 4.4 -14 30 4.2 -12 25 4.0 -10 20 3.8 -8 15 -6 3.6 10 -4 3.4 5 -2 3.2 0 0 3.0 0 0.5 1.0 1.5 2.0 2.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 100 125 OUTPUT LOW VOLTAGE (V) OUTPUT HIGH VOLTAGE (V) TEMPERATURE (°C) RECEIVER OUTPUT LOW VOLTAGE vs. DRIVER OUTPUT CURRENT vs. DRIVER DIFFERENTIAL OUTPUT VOLTAGE TEMPERATURE DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE 0.9 90 2.4 0.8 IRO = 8mA 80 2.3 R = 54Ω 0.7 70 2.2 0.6 60 2.1 0.5 50 2.0 0.4 40 1.9 0.3 30 1.8 0.2 20 1.7 0.1 10 1.6 0 0 1.5 -50 -25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) DIFFERENTIAL OUTPUT VOLTAGE (V) TEMPERATURE (°C) _______________________________________________________________________________________ 5 OUTPUT LOW VOLTAGE (V) OUTPUT CURRENT (mA) MAX481-04 MAX481-01 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) MAX481-05 MAX481-02 DIFFERENTIAL OUTPUT VOLTAGE (V) OUTPUT HIGH VOLTAGE (V) MAX481-06 MAX481-03 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers ____________________________Typical Operating Characteristics (continued) (VCC = 5V, TA = +25°C, unless otherwise noted.) OUTPUT CURRENT vs. OUTPUT CURRENT vs. MAX481/MAX485/MAX490/MAX491 DRIVER OUTPUT LOW VOLTAGE DRIVER OUTPUT HIGH VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 140 -120 600 MAX481/MAX485; DE = VCC, RE = X 120 -100 500 100 -80 400 80 -60 300 60 MAX485; DE = 0, RE = X, MAX481; DE = RE = 0 -40 200 40 MAX490/MAX491; DE = RE = X -20 20 100 MAX481; DE = 0, RE = VCC 0 0 0 0 2 4 6 8 10 12 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 OUTPUT LOW VOLTAGE (V) OUTPUT HIGH VOLTAGE (V) TEMPERATURE (°C) MAX483/MAX487–MAX489 MAX1487 SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE 600 600 500 500 400 400MAX483; DE = VCC, RE = X MAX1487; DE = VCC, RE = X 300 300 MAX487; DE = VCC, RE = X 200 200MAX483/MAX487; DE = RE = 0, MAX1487; DE = 0V, RE = X MAX488/MAX489; DE = RE = X 100 100 MAX483/MAX487; DE = 0, RE = VCC 0 0 -50 -25 0 25 50 75 100 125 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) 6 _______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 OUTPUT CURRENT (mA) SUPPLY CURRENT (µA) MAX481-07 OUTPUT CURRENT (mA) MAX481-12 SUPPLY CURRENT (µA) MAX481-08 SUPPLY CURRENT (µA) MAX481-13 MAX481-11 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers ______________________________________________________________Pin Description PIN MAX481/MAX483/ MAX488/ MAX489/ NAME FUNCTION MAX485/MAX487/ NAME FUNCTION MAX490 MAX491 MAX1487 DIP/SO µMAX DIP/SO µMAX DIP/SO Receiver Output: If A > B by 200mV, RO will be high; 1 3 2 4 2 RO If A < B by 200mV, RO will be low. Receiver Output Enable. RO is enabled when RE is low; RO is 2 4 — — 3 RE high impedance when RE is high. Driver Output Enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. If 3 5 — — 4 DE the driver outputs are enabled, the parts function as line drivers. While they are high impedance, they function as line receivers if RE is low. Driver Input. A low on DI forces output Y low and output Z high. 4 6 3 5 5 DI Similarly, a high on DI forces output Y high and output Z low. 5 7 4 6 6, 7 GND Ground — — 5 7 9 Y Noninverting Driver Output — — 6 8 10 Z Inverting Driver Output 6 8 — — — A Noninverting Receiver Input and Noninverting Driver Output — — 8 2 12 A Noninverting Receiver Input 7 1 — — — B Inverting Receiver Input and Inverting Driver Output — — 7 1 11 B Inverting Receiver Input 8 2 1 3 14 VCC Positive Supply: 4.75V ≤ VCC ≤ 5.25V — — — — 1, 8, 13 N.C. No Connect—not internally connected TOP VIEW RO 1 R 8 VCC MAX481 RE 2 MAX4837 B MAX485 DE DE 3 6 A MAX487 MAX1487 DI 4 D 5 GND RO 1 R 8 V DI CC D RE 2 7 B B DIP/SO Rt Rt DE 3 6 A A RO B 1 8 A DI 4 D 5 GND R VCC 2 MAX481 7 GND RE RO 3 MAX483MAX485 6 DI RE 4 MAX487 5 DE MAX1487 NOTE: PIN LABELS Y AND Z ON TIMING, TEST, AND WAVEFORM DIAGRAMS REFER TO PINS A AND B WHEN DE IS HIGH. µMAX TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE. Figure 1. MAX481/MAX483/MAX485/MAX487/MAX1487 Pin Configuration and Typical Operating Circuit _______________________________________________________________________________________ 7 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers TOP VIEW VCC VCC VCC 1 R 8 A 1 MAX488 RO 2 7 B MAX490 DI 3 6 Z 5 Y 3 GND 4 D 5 Y DI D Rt6 Z R RO DIP/SO 8 A 2 Rt B 1 8 Z RO R 7 D DI A B2 MAX488 7 Y VCC 3 MAX490 6 GND 4 RO 4 5 DI GND GND µMAX NOTE: TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE. Figure 2. MAX488/MAX490 Pin Configuration and Typical Operating Circuit TOP VIEW DE VCC VCC RE 4 14 MAX489 MAX491 N.C. 1 14 VCC 9 Y RO 2 R 13 N.C. DI 5 D Rt10 R RO RE 3 12 A Z DE 4 11 B 12 A DI 5 10 Z 2RO Rt D R 11 D DI GND 6 9 Y B 1, 8, 13 GND 7 8 N.C. NC 3 6, 7 DIP/SO RE GND GND DE Figure 3. MAX489/MAX491 Pin Configuration and Typical Operating Circuit __________Applications Information MAX487/MAX1487: The MAX481/MAX483/MAX485/MAX487–MAX491 and 128 Transceivers on the Bus1 MAX1487 are low-power transceivers for RS-485 and RS- The 48kΩ, /4-unit-load receiver input impedance of the 422 communications. The MAX481, MAX485, MAX490, MAX487 and MAX1487 allows up to 128 transceivers MAX491, and MAX1487 can transmit and receive at data on a bus, compared to the 1-unit load (12kΩ input rates up to 2.5Mbps, while the MAX483, MAX487, impedance) of standard RS-485 drivers (32 trans- MAX488, and MAX489 are specified for data rates up to ceivers maximum). Any combination of MAX487/ 250kbps. The MAX488–MAX491 are full-duplex trans- MAX1487 and other RS-485 transceivers with a total of ceivers while the MAX481, MAX483, MAX485, MAX487, 32 unit loads or less can be put on the bus. The and MAX1487 are half-duplex. In addition, Driver Enable MAX481/MAX483/MAX485 and MAX488–MAX491 have (DE) and Receiver Enable (RE) pins are included on the standard 12kΩ Receiver Input impedance. MAX481, MAX483, MAX485, MAX487, MAX489, MAX491, and MAX1487. When disabled, the driver and receiver outputs are high impedance. 8 _______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers _________________________________________________________________Test Circuits Y R TEST POINT 1kΩ RECEIVER VCC OUTPUT S1 VOD CRL 1kΩ 15pF R VOC Z S2 Figure 4. Driver DC Test Load Figure 5. Receiver Timing Test Load 3V VCC DE CL1 500Ω S1 A OUTPUT Y R RO UNDER TESTDI DIFF VID CL B Z RE S2 CL2 Figure 6. Driver/Receiver Timing Test Circuit Figure 7. Driver Timing Test Load MAX483/MAX487/MAX488/MAX489: monics with large amplitudes are evident. Figure 13 Reduced EMI and Reflections shows the same information displayed for a MAX483, The MAX483 and MAX487–MAX489 are slew-rate limit- MAX487, MAX488, or MAX489 transmitting under the ed, minimizing EMI and reducing reflections caused by same conditions. Figure 13’s high-frequency harmonics improperly terminated cables. Figure 12 shows the dri- have much lower amplitudes, and the potential for EMI ver output waveform and its Fourier analysis of a is significantly reduced. 150kHz signal transmitted by a MAX481, MAX485, MAX490, MAX491, or MAX1487. High-frequency har- _______________________________________________________________________________________ 9 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers _______________________________________________________Switching Waveforms 3V 3V DI 1.5V 1.5V DE 1.5V 1.5V 0V 0V tPLH tPHL 1/2 VO tZL(SHDN), tZL tLZ Z Y, Z VO 2.3V V OUTPUT NORMALLY LOW VOL +0.5V Y OL 1/2 VO VDIFF = V (Y) - V (Z) OUTPUT NORMALLY HIGH V Y, Z V ODIFF 0V 90% 90% 2.3V VOH -0.5V -V 10% 10% 0V O tR tF tZH(SHDN), tZH tHZ tSKEW = | tPLH - tPHL | Figure 8. Driver Propagation Delays Figure 9. Driver Enable and Disable Times (except MAX488 and MAX490) 3V RE 1.5V 1.5V 0V VOH RO tZL(SHDN), tZL tLZ VOL 1.5V OUTPUT 1.5V VCC RO 1.5V t t OUTPUT NORMALLY LOW VOL + 0.5V A-B V PHL PLH ID -VID 0V INPUT 0V OUTPUT NORMALLY HIGH RO 1.5V VOH - 0.5V 0V tZH(SHDN), tZH tHZ Figure 10. Receiver Propagation Delays Figure 11. Receiver Enable and Disable Times (except MAX488 and MAX490) _________________Function Tables (MAX481/MAX483/MAX485/MAX487/MAX1487) Table 1. Transmitting Table 2. Receiving INPUTS OUTPUTS INPUTS OUTPUT RE DE DI Z Y RE DE A-B RO X 1 1 0 1 0 0 > +0.2V 1 X 1 0 1 0 0 0 < -0.2V 0 0 0 X High-Z High-Z 0 0 Inputs open 1 1 0 X High-Z* High-Z* 1 0 X High-Z* X = Don't care X = Don't care High-Z = High impedance High-Z = High impedance * Shutdown mode for MAX481/MAX483/MAX487 * Shutdown mode for MAX481/MAX483/MAX487 10 ______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 10dB/div 10dB/div 0Hz 5MHz 0Hz 5MHz 500kHz/div 500kHz/div Figure 12. Driver Output Waveform and FFT Plot of MAX481/ Figure 13. Driver Output Waveform and FFT Plot of MAX483/ MAX485/MAX490/MAX491/MAX1487 Transmitting a 150kHz MAX487–MAX489 Transmitting a 150kHz Signal Signal Low-Power Shutdown Mode Driver Output Protection (MAX481/MAX483/MAX487) Excessive output current and power dissipation caused A low-power shutdown mode is initiated by bringing by faults or by bus contention are prevented by two both RE high and DE low. The devices will not shut mechanisms. A foldback current limit on the output down unless both the driver and receiver are disabled. stage provides immediate protection against short cir- In shutdown, the devices typically draw only 0.1µA of cuits over the whole common-mode voltage range (see supply current. Typical Operating Characteristics). In addition, a ther- RE and DE may be driven simultaneously; the parts are mal shutdown circuit forces the driver outputs into a guaranteed not to enter shutdown if RE is high and DE high-impedance state if the die temperature rises is low for less than 50ns. If the inputs are in this state excessively. for at least 600ns, the parts are guaranteed to enter Propagation Delay shutdown. Many digital encoding schemes depend on the differ- For the MAX481, MAX483, and MAX487, the tZH and ence between the driver and receiver propagation tZL enable times assume the part was not in the low- delay times. Typical propagation delays are shown in power shutdown state (the MAX485/MAX488–MAX491 Figures 15–18 using Figure 14’s test circuit. and MAX1487 can not be shut down). The tZH(SHDN) The difference in receiver delay times, | tPLH - tPHL |, is and tZL(SHDN) enable times assume the parts were shut typically under 13ns for the MAX481, MAX485, down (see Electrical Characteristics). MAX490, MAX491, and MAX1487 and is typically less It takes the drivers and receivers longer to become than 100ns for the MAX483 and MAX487–MAX489. enabled from the low-power shutdown state The driver skew times are typically 5ns (10ns max) for (tZH(SHDN), tZL(SHDN)) than from the operating mo–—d–e the MAX481, MAX485, MAX490, MAX491, and (tZH, tZL). (The parts are in operating mode if the RE , MAX1487, and are typically 100ns (800ns max) for the DE inputs equal a logical 0,1 or 1,1 or 0, 0.) MAX483 and MAX487–MAX489. ______________________________________________________________________________________ 11 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 100pF Z B TTL IN RECEIVER t , t < 6ns D RR F OUT Y R = 54Ω A 100pF Figure 14. Receiver Propagation Delay Test Circuit A B 500mV/div VCC = 5V TA = +25°C 500mV/div VCC = 5V TA = +25°C B A RO 2V/div 2V/div RO 20ns/div 20ns/div Figure 15. MAX481/MAX485/MAX490/MAX491/MAX1487 Figure 16. MAX481/MAX485/MAX490/MAX491/MAX1487 Receiver tPHL Receiver tPLH A B 500mV/div VCC = 5V 500mV/div VCC = 5V TA = +25°C TA = +25°C B A RO 2V/div 2V/div RO 400ns/div 400ns/div Figure 17. MAX483, MAX487–MAX489 Receiver tPHL Figure 18. MAX483, MAX487–MAX489 Receiver tPLH 12 ______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Line Length vs. Data Rate Figures 21 and 22 show typical network applications The RS-485/RS-422 standard covers line lengths up to circuits. These parts can also be used as l ine 4000 feet. For line lengths greater than 4000 feet, see repeaters, with cable lengths longer than 4000 feet, as Figure 23. shown in Figure 23. Figures 19 and 20 show the system differential voltage To minimize reflections, the line should be terminated at for the parts driving 4000 feet of 26AWG twisted-pair both ends in its characteristic impedance, and stub wire at 110kHz into 120Ω loads. lengths off the main line should be kept as short as possi- ble. The slew-rate-limited MAX483 and MAX487–MAX489 Typical Applications are more tolerant of imperfect termination. The MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 transceivers are designed for bidirectional data communications on multipoint bus transmission lines. DI 5V DI 5V 0V 0V 1V 1V VY-VZ 0V VY-VZ 0V -1V -1V RO 5V RO 5V 0V 0V 2µs/div 2µs/div Figure 19. MAX481/MAX485/MAX490/MAX491/MAX1487 System Figure 20. MAX483, MAX487–MAX489 System Differential Differential Voltage at 110kHz Driving 4000ft of Cable Voltage at 110kHz Driving 4000ft of Cable 120Ω 120Ω DE B B DI D D DI DE A B A B A A RO R R RO RE RE R R MAX481 D D MAX483 MAX485 MAX487 DI DE RO RE DI DE RO RE MAX1487 Figure 21. MAX481/MAX483/MAX485/MAX487/MAX1487 Typical Half-Duplex RS-485 Network ______________________________________________________________________________________ 13 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers A Y 120Ω 120Ω RO R D DI RE B Z DE DE Z B RE DI D 120Ω 120Ω R RO Y Y Z B A Y Z B A A R R D D MAX489 MAX491 DI DE RE RO DI DE RE RO NOTE: RE AND DE ON MAX489/MAX491 ONLY. Figure 22. MAX488–MAX491 Full-Duplex RS-485 Network Isolated RS-485 For isolated RS-485 applications, see the MAX253 and MAX488–MAX491 MAX1480 data sheets. A RO R 120ΩB DATA INRE DE Z DI D 120Ω DATA OUTY NOTE: RE AND DE ON MAX489/MAX491 ONLY. Figure 23. Line Repeater for MAX488–MAX491 14 ______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers _______________Ordering Information __Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE PART TEMP. RANGE PIN-PACKAGE MAX481CPA 0°C to +70°C 8 Plastic DIP MAX490CPA 0°C to +70°C 8 Plastic DIP MAX481CSA 0°C to +70°C 8 SO MAX490CSA 0°C to +70°C 8 SO MAX481CUA 0°C to +70°C 8 µMAX MAX490CUA 0°C to +70°C 8 µMAX MAX481C/D 0°C to +70°C Dice* MAX490C/D 0°C to +70°C Dice* MAX481EPA -40°C to +85°C 8 Plastic DIP MAX490EPA -40°C to +85°C 8 Plastic DIP MAX481ESA -40°C to +85°C 8 SO MAX490ESA -40°C to +85°C 8 SO MAX481MJA -55°C to +125°C 8 CERDIP MAX490MJA -55°C to +125°C 8 CERDIP MAX483CPA 0°C to +70°C 8 Plastic DIP MAX491CPD 0°C to +70°C 14 Plastic DIP MAX483CSA 0°C to +70°C 8 SO MAX491CSD 0°C to +70°C 14 SO MAX483CUA 0°C to +70°C 8 µMAX MAX491C/D 0°C to +70°C Dice* MAX491EPD -40°C to +85°C 14 Plastic DIP MAX483C/D 0°C to +70°C Dice* MAX491ESD -40°C to +85°C 14 SO MAX483EPA -40°C to +85°C 8 Plastic DIP MAX491MJD -55°C to +125°C 14 CERDIP MAX483ESA -40°C to +85°C 8 SO MAX1487CPA 0°C to +70°C 8 Plastic DIP MAX483MJA -55°C to +125°C 8 CERDIP MAX1487CSA 0°C to +70°C 8 SO MAX485CPA 0°C to +70°C 8 Plastic DIP MAX1487CUA 0°C to +70°C 8 µMAX MAX485CSA 0°C to +70°C 8 SO MAX1487C/D 0°C to +70°C Dice* MAX485CUA 0°C to +70°C 8 µMAX MAX1487EPA -40°C to +85°C 8 Plastic DIP MAX485C/D 0°C to +70°C Dice* MAX1487ESA -40°C to +85°C 8 SO MAX485EPA -40°C to +85°C 8 Plastic DIP MAX1487MJA -55°C to +125°C 8 CERDIP MAX485ESA -40°C to +85°C 8 SO MAX485MJA -55°C to +125°C 8 CERDIP * Contact factory for dice specifications. MAX487CPA 0°C to +70°C 8 Plastic DIP MAX487CSA 0°C to +70°C 8 SO MAX487CUA 0°C to +70°C 8 µMAX MAX487C/D 0°C to +70°C Dice* _________________Chip Topographies MAX487EPA -40°C to +85°C 8 Plastic DIP MAX481/MAX483/MAX485/MAX487/MAX1487 MAX487ESA -40°C to +85°C 8 SO MAX487MJA -55°C to +125°C 8 CERDIP VCC MAX488CPA 0°C to +70°C 8 Plastic DIP MAX488CSA 0°C to +70°C 8 SO RO N.C. MAX488CUA 0°C to +70°C 8 µMAX N.C. MAX488C/D 0°C to +70°C Dice* RE 0.054" MAX488EPA -40°C to +85°C 8 Plastic DIP B (1.372mm) MAX488ESA -40°C to +85°C 8 SO DE MAX488MJA -55°C to +125°C 8 CERDIP DI A MAX489CPD 0°C to +70°C 14 Plastic DIP MAX489CSD 0°C to +70°C 14 SO GND MAX489C/D 0°C to +70°C Dice* 0.080" MAX489EPD -40°C to +85°C 14 Plastic DIP (2.032mm) MAX489ESD -40°C to +85°C 14 SO MAX489MJD -55°C to +125°C 14 CERDIP ______________________________________________________________________________________ 15 MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers _____________________________________________Chip Topographies (continued) MAX488/MAX490 MAX489/MAX491 VCC VCC RO A RO A B B N.C. 0.054" RE 0.054" Z Z(1.372mm) (1.372mm) N.C. DE Y DI DI Y GND GND 0.080" 0.080" (2.032mm) (2.032mm) TRANSISTOR COUNT: 248 SUBSTRATE CONNECTED TO GND 16 ______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 N A1 0.004 0.010 0.10 0.25 B 0.014 0.019 0.35 0.49 C 0.007 0.010 0.19 0.25 e 0.050 BSC 1.27 BSC E 0.150 0.157 3.80 4.00 E H H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 VARIATIONS: 1 INCHES MILLIMETERS TOP VIEW DIM MIN MAX MIN MAX N MS012 D 0.189 0.197 4.80 5.00 8 AA D 0.337 0.344 8.55 8.75 14 AB D 0.386 0.394 9.80 10.00 16 AC D A C e B A1 0∞-8∞ L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .150" SOIC APPROVAL DOCUMENT CONTROL NO. REV. 1 21-0041 B 1 ______________________________________________________________________________________ 17 SOICN .EPS MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 4X S 8 8 INCHES MILLIMETERS DIM MIN MAX MIN MAX A - 0.043 - 1.10 A1 0.002 0.006 0.05 0.15 A2 0.030 0.037 0.75 0.95 b 0.010 0.014 0.25 0.36 E H ÿ 0.50±0.1 c 0.005 0.007 0.13 0.18 D 0.116 0.120 2.95 3.05 0.6±0.1 e 0.0256 BSC 0.65 BSC E 0.116 0.120 2.95 3.05 H 0.188 0.198 4.78 5.03 L 0.016 0.026 0.41 0.66 1 1 0.6±0.1 α 0∞ 6∞ 0∞ 6∞ D BOTTOM VIEW S 0.0207 BSC 0.5250 BSC TOP VIEW A2 A1 A c α e b L FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 8L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. REV. 1 21-0036 J 1 18 ______________________________________________________________________________________ MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 8LUMAXD.EPS Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 PDIPN.EPS MAX481/MAX483/MAX485/MAX487–MAX491 MOP-AL204A Parallel Display Specifications Revision 1.0 Revision History Revision Description Author 1.0 Initial Release Clark 0.2 Updates as per issue #333 Clark 0.1 Initial Draft Clark 1 Contents Revision History ............................................................................................................................................ 1 Contents ........................................................................................................................................................ 2 Features ........................................................................................................................................................ 3 Hardware ...................................................................................................................................................... 3 Drawing ..................................................................................................................................................... 3 Interface .................................................................................................................................................... 3 Instructions ................................................................................................................................................... 4 Outline ...................................................................................................................................................... 4 Instruction Table ....................................................................................................................................... 5 Character ROM.......................................................................................................................................... 6 Character RAM .......................................................................................................................................... 7 Timing Characteristics ............................................................................................................................... 7 Initialization............................................................................................................................................... 8 Specifications ................................................................................................................................................ 9 Electrical .................................................................................................................................................... 9 Optical ....................................................................................................................................................... 9 Environmental ........................................................................................................................................... 9 Troubleshooting .......................................................................................................................................... 10 Power ...................................................................................................................................................... 10 Display ..................................................................................................................................................... 10 Communication ....................................................................................................................................... 10 Precautions ............................................................................................................................................. 10 Ordering ...................................................................................................................................................... 11 Part Numbering Scheme ......................................................................................................................... 11 Options .................................................................................................................................................... 11 Contact ........................................................................................................................................................ 11 2 Features The Matrix Orbital Parallel display series offers a low cost display solution utilizing an industry standard communication interface for simple integration into a wide variety of new and existing applications. The Light Emitting Diode backlight with configurable brightness and voltage controlled contrast allows the MOP Liquid Crystal Display line to offer a professional display solution with low power impact for any project. The standard alphanumeric font set also allows up to eight custom characters to be saved in display Random Access Memory for a custom design touch. Hardware Drawing 10.0 P2.54X(16-1)=38.10 15.0(MAX.) 3.55 9.4±0.5 16- 1.0 2.95 16 0.551 4- 2.5 0.05 1.6±0.1 70.40(A.A.) 76.0(V.A.) 93.0 2.5 98.0±0.5 Figure 1: MOP-AL204A Mechanical Drawing Interface Table 1: Display Control Table 2: Parallel Data Pin Symbol Description Pin Symbol Description 1 VSS Ground 7 DB0 *Data bit 0 2 VDD Supply Voltage for Logic 8 DB1 *Data bit 1 3 V0 Supply Voltage for LCD (Contrast) 9 DB2 *Data bit 2 4 RS Register Select 10 DB3 *Data bit 3 5 R/W Read/Write 11 DB4 Data bit 4 6 CE Chip Enable 12 DB5 Data bit 5 15 LED(+) Anode of LED Backlight 13 DB6 Data bit 6 16 LED(-) Cathode of LED Backlight 14 DB7 Data bit 7 *Note: Not used in 4-bit mode 3 60.0±0.5 55.0 2.5 40.0 25.2(V.A.) 20.80(A.A.) 2.5 5.35 4.75 0.55 0.05 Instructions Outline The MOP line is controlled using a standard HD44780 compliant controller. The display is enabled by pulling the Chip Enable (CE) pin high, communication to and from the device is controlled using the Read/Write (R/W) input, and one of two available 8-bit registers are selected via the Register Select (RS) line. Using Register Select, either the Instruction Register (IR) or Data Register (DR) is selected by toggling RS low or high respectively. While executing from the IR, the display will pull the Most Significant Bit of the data bus, DB7, high. While this Busy Flag (BF) is set, any instructions sent to the unit will be ignored. The status of this flag and the current position of the Address Counter (AC) can be obtained by performing a read operation on the instruction register at any time. Table 3: Register Selection RS R/W Operation 0 0 IR write as an internal operation (display clear, etc.) 0 1 Read busy flag (DB7) and address counter (DB0 to DB6) 1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM) 1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR) When writing for the DR, one of two locations can be chosen using the AC. The value provided to the AC when executing a set address command differentiates these locations. The AC is automatically decremented or incremented after a read or a write. DDRAM provides eighty bytes of display memory to all displays. Memory outside the bounds of the display area can be used as general RAM. DDRAM addressing begins at the top left of the display with a value of 0, addresses then increment from left to right then down once a row is filled. Table 4: One Line Addressing Table 5: Two Line Addressing Table 6: Four Line Addressing Position 1 2 ... 80 Position 1 2 ... 40 Position 1 2 ... 20 DDRAM Address 00 01 ... 4F DDRAM 00 01 ... 27 00 01 ... 13 Address 40 41 ... 67 DDRAM 40 41 ... 53 Address 14 15 ... 27 54 55 ... 67 CGRAM provides eight custom characters that can be created by writing to CGRAM locations then displayed using the first eight CGROM character codes, as seen in the character ROM table below. Characters are sent to the display by performing a write operation on the DR using the correct character address within CGROM. Instructions are issued by writing to the IR; a complete list is available below. 4 Instruction Table Table 7: Parallel Instruction Table Instruction Code Instruction Description RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Write “20H” to all DDRAM locations, set 0 0 0 0 0 0 0 0 0 1 DDRAM address to “00H”, return cursor Display to its original position, and set I/D to “1”. Return Set DDRAM address to “00H” and return 0 0 0 0 0 0 0 0 1 － cursor to its original position if shifted. Home The contents of DDRAM are not changed. Assign cursor moving direction and enable the shift of entire display. DDRAM Entry Mode and CRAM addresses are incremented 0 0 0 0 0 0 0 1 I/D SH and cursor moves right when I/D is set to Set “1”, the opposite is true when reset to “0”. Setting SH to “1” causes the entire display to shift affecting only DDRAM. Set display (D), cursor (C), and blinking of Display cursor (B) on/off control bit. Setting D, C, ON/OFF 0 0 0 0 0 0 1 D C B or B to “1” will cause the display, Control underline cursor, or blinking cursor to turn on, the opposite is true for reset. Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. Setting S/L to Cursor or “1” will shift the screen horizontally while 0 0 0 0 0 1 S/C R/L － － Display Shift the opposite will move the cursor through all screen positions. Setting R/L to “1” will shift right immediately. AC and DDRAM are not altered. Set interface data length, numbers of display line and, display font type. Setting DL to “1” specifies 8-bit mode, “0” Function Set 0 0 0 0 1 DL N F － － 4-bit. Setting N to “1” permits a multi- line display, “0” a single. Resetting F to “0” indicates a 5x8 dot character. Set CGRAM 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. Address Set DDRAM 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. Address Read Busy Read the status of the display controller Flag and 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 through the BF Bit. The contents of Address address counter can also be read. Write data into internal RAM Write Data (DDRAM/CGRAM), location is determined 1 0 D7 D6 D5 D4 D3 D2 D1 D0 to RAM by the AC. AC and display shift are adjusted as specified. Read data from internal RAM Read Data (DDRAM/CGRAM), location is determined 1 1 D7 D6 D5 D4 D3 D2 D1 D0 from RAM by the AC, set command is recommended previous to this. Only AC is adjusted. 5 Character ROM The character generator ROM stores up to two hundred fifty-six 5 8 dot character patterns from 8-bit character codes. The first eight characters are reserved for custom characters saved in CGRAM. Figure 2: European Character Set 6 Character RAM CGRAM allows the creation of up to Table 8:Relationship between CGRAM Addresses, eight 5x8 character patterns. Eight Character Codes (DDRAM Data) and Character Patterns (CGRAM Data) bytes are assigned to each character address, the least significant five bits of which represent the five pixel columns. Pixels are activated by setting the bit in their position in CGRAM to “1”. Each character has eight addresses in CGRAM corresponding to each of its eight pixel rows. The highest three bits represent the character address in DDRAM. The lowest three bits of this address represent the row positions beginning with 0 at the top. The last row will be logically OR’d with the cursor when it is active. Finally, each character can be referenced in DDRAM and written to the screen using its eight bit address. Note: * Indicates no effect. Timing Characteristics Table 9: Read and Write Operation Specifications Write Read Item Symbol Min Typ Max Min Typ Max Unit Enable cycle time tcycE 1200 － － 1200 － － ns Enable pulse width (high level) PWEH 140 － － 140 － － ns Enable rise/fall time tEr,tEf － － 25 － － 25 ns Address set-up time (RS, R/W to E) tAS 0 － － 0 － － ns Address hold time tAH 10 － － 10 － － ns Data set-up time tDS 40 － － － － 100 ns Data hold time tH 10 － － 10 － － ns Conditions: Ta=25℃, VDD=5.0± 0.5V Figure 3: Write Timing Waveform Figure 4: Read Timing Waveform 7 Initialization Before beginning any application, it is recommended that all display settings be initialized. Below are algorithms for initializing the display in both 8-bit and 4-bit communication modes. Before the first wait condition, please allow Vcc to rise to 2.7V then wait 40ms. During the three function set commands that follow, note that the busy flag cannot be checked; it becomes available in the last block. The unit will always expect a total of 8 bits to be sent, so note the structure used in four bit mode. The last initialization block will set the number of lines and character font as specified, turn the display off, issue the display clear command, and finally set the entry mode as desired. Figure 5: 8-bit Initialization Figure 6: 4-bit Initialization Note: * Indicates do not care condition. 8 Specifications Electrical Table 10: Electrical Characteristics Item Symbol Min Typ Max Unit Supply Voltage For Logic VDD 4.5 5.0 5.5 V Supply Voltage For LCD (Contrast) V0 -13.5 － VDD V Input High Voltage VIH 0.7 VDD － VDD V Input Low Voltage VIL VSS － 0.3 VDD V Supply Current (VDD=5V) IDD 0.7 1.75 1.5 mA Supply Voltage of Red Backlight (36 Die) VLED 3.5 3.9 4.1 V Supply Current of Red Backlight (36Die) ILED 0 － 180 mA Supply Voltage of Yellow-Green Backlight (36 Die) VLED 4.0 4.2 4.4 V Supply Current of Yellow-Green Backlight (36 Die) ILED 0 － 180 mA Supply Voltage of White Backlight (2 Die) VLED 3.8 4.0 4.2 V Supply Current of White Backlight (2 Die) ILED 0 － 30 mA Optical Table 11: Display Characteristics θ bθ f φ = 180° Item Dimension Unit θ l Number of Characters 20 Characters x 4 Lines － θ r Module dimension 98.0 x 60.0 x 15.0 mm View area 76.0 x 25.2 mm φ = 270° φ = 90° Active area 70.40 x 20.80 mm Character size 2.95 x 4.75 mm Character pitch 3.55 x 5.35 mm φ = 0° Dot size 0.55 x 0.55 mm Figure 7: Viewing Angle Definition Dot pitch 0.60 x 0.60 mm LCD type STN Non-selected Non-selected Conition Selected ConitionDuty 1/16 Conition View direction 12 o’clock Intensity Table 12: Viewing Characteristics 10％ Item Symbol Min Typ Max Unit 90％ (V)θ -20 － 35 deg 100％ View Angle (H)φ -30 － 30 deg Contrast Ratio CR － 3 － － T rise － － 250 ms Response Time Tr Tf T fall － － 250 ms Figure 8: Di[spposlaitiyv eR tyepsep] onse Time Environmental Table 13: Environmental Specifications Item Symbol Min Max Unit Operating Temp. Top -20 70 ℃ Storage Temp. Tstr -30 80 ℃ Note: Maximum 90% non-condensing humidity. 9 Troubleshooting Power For your MOP Display to function correctly, appropriate power must be applied, often as indicated by the backlight illuminating or a darkening of the character spaces. Please refer to the power diagram below and reference all voltages to the specifications provided. Figure 9: Single Supply Configuration Figure 10: Dual Supply Configuration Display If your display is powered successfully, the backlight or contrast should be evident. A lack of text could be the result of a high contrast voltage, lower V0. Also, ensure the expected DDRAM addresses are shown by moving the display to the home position. Communication When communication of either text or commands is interrupted, check all data and control pins for continuity. Ensure the display has been initialized correctly before sending information using the appropriate initialization algorithm. For 4-bit mode ensure D4-D7 are used. Finally, slow down communication and refer to timing diagrams and specifications for proper control flow. Precautions • Do not make extra holes on the display, modify its shape, or change the components. • Avoid applying excessive electrical shock to the module. • Do not drop, bend, twist, or disassemble the display. • Avoid operation outside absolute maximum ratings. • Solder only to the I/O terminals provided. • Store in an anti-static container within a clean environment. 10 Ordering Part Numbering Scheme Table 14: Parallel Part Numbering Scheme MOP A L 20 4 A B G F W 2 5 E 3 I N - - - - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Options Table 15: Parallel Part Options # Designator Options 1 Product Line MOP: Matrix Orbital Parallel Display 2 Display Type A: Alphanumeric 3 Screen Type L: Liquid Crystal Display 8: Eight Character Columns 16: Sixteen Character Columns 4 Display Columns 20: Twenty Character Columns 24: Twenty-Four Character Columns 40: Forty Character Columns 2: Two Character Rows 5 Display Rows 4: Four Character Rows A: A Form Factor B: B Form Factor 6 Display Form Factor C: C Form Factor F: F Form Factor 7 IC Package B: Chip on Board B: STN Positive Blue F: FFSTN Negative G: STN Positive Grey 8 LCD Glass Type T: FSTN Negative W: FSTN Positive Y: STN Positive Yellow F: Transflective 9 Polarizer Style T: Transmissive R: Red 10 Backlight Colour Y: Yellow-Green W: White 1: 6:00 11 Viewing Angle 2: 12:00 12 Controller 5: S6A0069 Compatible E: European 13 Character Set J: Japanese 14 Input Voltage 3: 5.0V 15 Temperature Range I: Industrial 16 Negative Voltage Generation N: None Provided Contact Sales Support Online Phone: 403.229.2737 Phone: 403.204.3750 Purchasing: www.matrixorbital.com Email: sales@matrixorbital.ca Email: support@matrixorbital.ca Support: www.matrixorbital.ca 11 WORLD-BEAM® Q12 Miniature self-contained photoelectric sensors in universal housing Features • Bright, visible red (640 nm) light source • Standard models available with 4-wire 2 m (6.5') or 9 m (30') cable or 3 or 4-wire 150 mm (6") pigtail with Pico-style M8 threaded connector • Solid-state, bipolar outputs: one current sourcing (PNP) and one current sinking (NPN) standard on 4-wire models • Single output solid-state PNP or NPN standard on Q3 models • Light Operate (L.O.) or Dark Operate (D.O.), depending on model • Models available with PFA chemical-resistant jacket (1200 psi washdown rated) for use in harsh environments (see Chemical-Resistant Models on page 3). • Compact 8 mm (0.31") housing mounts almost anywhere Standard Chemical-Resistant Model Model • Crosstalk-avoidance circuitry for multiple-sensor applications • LED status indicators for Power ON, Output Overload, Signal Received, and Marginal Signal Standard Models Sensing Mode Model* Range Output 640 nm Visible Red Q126E (emitter) N/A Q12AB6R Bipolar LO Q12RB6R Bipolar DO Opposed Effective Beam: 5.7 mm (0.22") Q12AP6RQ3 2 m (6.5') 1 PNP LO Q12RP6RQ3 1 PNP DO Q12AN6RQ3 1 NPN LO Q12RN6RQ3 1 NPN DO Q12AB6LP Bipolar LO Q12RB6LP Bipolar DO 640 nm Visible Red Polarized Q12AP6LPQ3 1 PNP LO 1 m** (40") Retro Q12RP6LPQ3 1 PNP DO Q12AN6LPQ3 1 NPN LO Q12RN6LPQ3 1 NPN DO P/N 119223 rev. G 8/2009 0 119223 9 Sensing Mode Model* Range Output 119223 Q12AB6LV Bipolar LO Q12RB6LV Bipolar DO 640 nm Visible Red Q12AP6LVQ3 1 PNP LO Retro 1.5 m** (59") Q12RP6LVQ3 1 PNP DO Q12AN6LVQ3 1 NPN LO Q12RN6LVQ3 1 NPN DO Performance based on use of 90% reflectance white test card. Q12AB6FF15 Bipolar LO Q12RB6FF15 Bipolar DO Q12AP6FF15Q3 15 mm (0.6") cutoff; 1 PNP LO Q12RP6FF15Q3 10 mm (0.4") focus 1 PNP DO Q12AN6FF15Q3 1 NPN LO Q12RN6FF15Q3 1 NPN DO Q12AB6FF30 Bipolar LO Q12RB6FF30 Bipolar DO Fixed-Field 640 nm Visible Red Q12AP6FF30Q3 30 mm (1.2") cutoff; 1 PNP LO Q12RP6FF30Q3 16 mm (0.63") focus 1 PNP DO Q12AN6FF30Q3 1 NPN LO Q12RN6FF30Q3 1 NPN DO Q12AB6FF50 Bipolar LO Q12RB6FF50 Bipolar DO Q12AP6FF50Q3 50 mm (2") cutoff 1 PNP LO Q12RP6FF50Q3 16 mm (0.63") focus 1 PNP DO Q12AN6FF50Q3 1 NPN LO Q12RN6FF50Q3 1 NPN DO * Q3 models: 3-pin Pico-style (M8 threaded) 150 mm (6") pigtail QD. Not available for bipolar models. Models with no suffix have standard 2 m (6.5') cables. • For 9 m (30') cable, add suffix “W/30” to the model number (e.g., Q126E W/30). • For 4-pin Pico-style (M8 threaded) 150 mm (6") pigtail QD, add suffix Q to the model number (e.g. Q126EQ). • For 4-pin Euro-style (M12 threaded) 150 mm (6") pigtail QD, add suffix Q5 to the model number (e.g. Q126EQ5). **Retroreflective range is specified using one model BRT-60X40C retroreflector. Actual sensing range may be more or less than specified, depending upon efficiency and reflective area of the retroreflector(s) used. 2 Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com P/N 119223 rev. G Tel: 763.544.3164 119223 Chemical-Resistant Models Sensing Mode Model* Range Output 640 nm Visible Red Q126ECR N/A Q12AB6RCR Bipolar LO Opposed Effective Beam: 5.7 mm (0.22") 1.5 m (4.9') Q12RB6RCR Bipolar DO Performance based on use of 90% reflectance white test card. Q12AB6FF15CR Bipolar LO 13 mm (0.5") cutoff; Q12RB6FF15CR 8 mm (0.3") focus Bipolar DO Fixed-Field 640 nm Visible Red Q12AB6FF30CR Bipolar LO28 mm (1.1") cutoff; Q12RB6FF30CR 14 mm (0.6") focus Bipolar DO Q12AB6FF50CR Bipolar LO 48 mm (1.9") cutoff; Q12RB6FF50CR 14 mm (0.6") focus Bipolar DO *Only standard 2 m (6.5') cables are available for chemical-resistant models. Indicator Features 1 • 1.Yellow and Green LEDs • Green ON steady: power to sensor is ON • Green flashing: output is overloaded • Yellow ON steady: received signal • Yellow flashing: marginal signal Figure 1. Features Chemical-Resistant models: LEDs are visible through translucent PFA jacket. Rated to 1200 psi washdown. P/N 119223 rev. G Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com 3 Tel: 763.544.3164 119223 Specifications Feature Description Sensing Beam 640 nm visible red Supply Voltage and Current 10 to 30V dc (10% max. ripple) @ 20 mA max current Supply Protection Circuitry Protected against reverse polarity and transient voltages Bipolar (1 NPN and 1 PNP) solid-state output or Single output (PNP or NPN), LO Output Configuration or DO, depending on model 50 mA total across all output(s) with overload and short circuit protection Output Ratings OFF-state leakage current: NPN: 200 µA PNP: 10 µA ON-state saturation voltage: NPN: 1.25V @ 50 mA PNP: 1.45V @ 50 mA Output Protection Circuitry Protected against false pulse on power-up, short-circuit protected Opposed Mode: 1.3 ms ON; 900 µs OFF Output Response Time All Other Modes: 700 µs ON/OFF NOTE: 120 ms delay on power-up; outputs do not conduct during this time. Repeatability 175 microseconds Opposed Mode: 385 Hz Switching Frequency All Other Modes: 715 Hz Indicators One Yellow and one Green LED (see Figure 1) Polarized Retro Models: Thermoplastic elastomer housing with glass lens All Other Standard Models: Thermoplastic elastomer housing with polycarbonate Construction lens Chemical-Resistant Models: Housing encased in PFA jacket; cable encased in 3/16" O.D. PFA tubing Standard Models: IEC IP67 Environmental Rating Chemical-Resistant Models: IEC IP67 (NEMA6) and PW12 1200 psi washdown per NEMA ICS5, Annex F-2002 Standard Models: 2 m (6.5') or 9 m (30') attached PVC cable, or 150 mm (6") Connections pigtail with M8 or M12 threaded connection Chemical-Resistant Models: 2 m (6.5') cable encased in 3/16" O.D. PFA tubing Operating temperature: -20° to +55° C (-4° to +131° F) Operating Conditions Storage temperature: -30° to +75° C (-22° to +167° F) Relative humidity: 95% max @ +50° C (+122° F) non-condensing Certifications 4 Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com P/N 119223 rev. G Tel: 763.544.3164 119223 Dimensions Standard Models 12.4 mm (0.49") M3 mounting screws included 8.0 mm (0.31") 15.0 mm Polarized Retro 4.7 mm (0.59") Models (0.19") 5.1 mm Emitter (opposed mode models) 23.1 mm (0.20") (0.91") 22 mm (0.86") Emitter (all other models) 3.4 mm 3.5 mm (0.13") (0.14") Ø 3 mm (0.12") max. torque 0.9 Nm (8 in-lbf) Chemical-Resistant Models 22.6 mm (0.89") 8.1 mm (0.32") 12.5 mm (0.49") Mounting hardware not included 5.9 mm (0.23") * When mounting by running a screw through both flanges without support between the flanges, 6.2 mm the max. torque applied should be 0.1 Nm (1 in-lbf). Ø 3.4 mm (0.13") 3.2 mm (0.13") (0.25") max. torque* 0.9 Nm (8 in-lbf) Emitter (opposed mode models) 15.0 mm (0.59") 28.8 mm (1.13") 10.7 mm (0.42") 8.6 mm (0.34") 4.7 mm 5.5 mm (0.22") (0.18") Emitter (all other models) 4.8 mm (0.19") O.D. Ø12.5 mm (0.49") PFA Tube 2 m (6.5') P/N 119223 rev. G Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com 5 Tel: 763.544.3164 119223 Performance Curves - Opposed Mode Excess Gain Beam Pattern 1000 E Q12.. X Opposed Mode 3 mm Q12.. 0.12" Opposed Mode C 100 2 mm 0.08"E 1 mm 0.04" S S 0 0Standard Chemical-Resistant Opposed 1 mm 0.04" G 10 2 mm 0.08" A I 3 mm Standard 0.12" N Chemical-Resistant 0 0.5 m 1 m 1.5 m 2 m 2.5 m 1 20" 40" 60" 80" 100" 0.01 m 0.1 m 1 m 10 m DISTANCE 0.033' 0.33' 3.3' 33' DISTANCE Performance Curves - Retro Mode Excess Gain Beam Pattern Performance based on use of a model BRT-60X40C retroreflector. 1000 E Q12.. 9 mm Q12.. 0.3" X Polarized Retro Polarized Retro C 6 mm 0.2" E 100 3 mm 0.1" Polarized S 0 0 S Retro 3 mm 0.1" G 10 6 mm 0.2" A 9 mm 0.3" I N 0 0.3 m 0.6 m 0.9 m 1.2 m 1.5 m 12" 24" 35" 47" 1 59" 0.01 m 0.1 m 1 m 10 m DISTANCE 0.03' 0.33' 3.3' 33' DISTANCE 1000 E Q12.. X Retroreflective 30 mm Q12.. 1.2" C Retroreflective E 100 20 mm 0.8" S 10 mm 0.4" S 0 0 Retro 10 mm 0.4"G 10 20 mm 0.8" A 30 mm 1.2" I N 0 0.3 m 0.6 m 0.9 m 1.2 m 1.5 m 1 12" 24" 35" 47" 59" 0.01 m 0.1 m 1 m 10 m DISTANCE 0.03' 0.33' 3.3' 33' DISTANCE 6 Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com P/N 119223 rev. G Tel: 763.544.3164 119223 Performance Curves - Fixed-Field Excess Gain Performance based on use of 90% reflectance white test card.* Standard Models: • Ø 0.4 mm spot size @ 10 mm focus 1000 Q12..FF15 E • Ø 1.5 mm spot size @ 15 mm cutoff X Fixed-Field C E 100 Chemical-Resistant Models: Fixed-Field – 15 mm SS Standard • Ø 0.4 mm spot size @ 8 mm focus G 10 A • Ø 1.5 mm spot size @ 13 mm cutoff I N Chemical-Resistant 1 * Using 18% gray test card: cutoff distance will be 1 mm 10 mm 100 mm 1000 mm 0.04" 0.4" 4.0" 40.0" 95% of value shown. DISTANCE * Using 6% black test card: cutoff distance will be 90% of value shown. Standard Models: • Ø 0.5 mm spot size @ 16 mm focus 1000 Q12..FF30 E • Ø 3.0 mm spot size @ 30 mm cutoff X Fixed-Field C E 100 Chemical-Resistant Models: S S Standard Fixed-Field – 30 mm • Ø 0.5 mm spot size @ 14 mm focus G 10 A • Ø 3.0 mm spot size @ 28 mm cutoff I N Chemical-Resistant * Using 18% gray test card: cutoff distance will be 1 1 mm 10 mm 100 mm 1000 mm 90% of value shown. 0.04" 0.4" 4.0" 40.0" DISTANCE * Using 6% black test card: cutoff distance will be 80% of value shown. Standard Models: • Ø 0.5 mm spot size @ 16 mm focus • Ø 6.5 mm spot size @ 50 mm cutoff 1000 * Using 18% gray test card: cutoff distance will be Q12..FF50 E 80% of value shown. X Fixed-Field Mode C E 100 * Using 6% black test card: cutoff distance will be S S Standard 60% of value shown. Fixed-Field – 50 mm G 10 A Chemical-Resistant Models: I Chemical-Resistant N • Ø 0.5 mm spot size @ 14 mm focus 1 1 mm 10 mm 100 mm 1000 mm • Ø 6.5 mm spot size @ 48 mm cutoff 0.04" 0.4" 4.0" 40.0" DISTANCE * Using 18% gray test card: cutoff distance will be 70% of value shown. * Using 6% black test card: cutoff distance will be 50% of value shown. Focus and spot sizes are typical. Legend: ––––––– Standard models – – – – – Chemical-Resistant models P/N 119223 rev. G Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com 7 Tel: 763.544.3164 119223 Hookups Emitters Bipolar Models Wiring Key: 1 + 1 = Brown 1 4-Pin+ 3 10-30V dc – 2 = Whi1te= Brown 10-30V dc 1 = Brown 2 = White 3 = Blue 2 3 = Blue 3 Load– 3 = Blue4 = Black 4 Load 4 = Black PNP Models NPN Models 1 + 33-Pin – 3-Pin 3 10-30V dc 1 = Brown 1 10-30V dc– + 1 = Brown 3 = Blue 3 = Blue 4 4 Load 4 = Black Load 4 = Black Cabled hookups only are shown. Hookups for QD models are functionally identical. (Emitters have no connection to black and white.) NOTE: Please observe proper ESD precautions (grounding) when connecting QD models. Quick-Disconnect (QD) Cordsets Style Model Length Dimensions Pinout Female 4 2 3 1 34.7 mm M8 x 1 4-pin Pico-style (1.37")PKG4M-2 2 m (6.5') straight with M8 9.6 mm threads PKG4M-9 9 m (30') (0.38") Wiring Key: 1 = Brown 2 = White 3 = Blue 4 = Black 4-Pin Pico 4-Pin 4-Wire 1 = Brown 2 = White 3 = Blue 4 = Black 8 Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com P/N 119223 rev. G Tel: 763.544.3164 119223 Quick-Disconnect (QD) Cordsets Style Model Length Dimensions Pinout Female 4 3 1 34.7 mm M8 x 1 3-pin Pico-style (1.37")PKG3M-2 2 m (6.5') straight with M8 9.6 mm threads PKG3M-9 9 m (30') (0.38") Wiring Key: 1 = Brown 3 = Blue 4 = Black 4-Pin Pico 4-Pin 4-Wire Mounting Brackets 1 = Brown 2 = White SMBQ12T SMBQ12A 3 = Blue 4 = Black • Right-angle bracket for • Adjustable right-angle use with standard Q12 bracket for use with models standard Q12 models • 300 series stainless steel, • 300 series stainless steel, 20 gauge 20 gauge Ø 3.2 mm Ø 3.2 mm (Ø 0.26") (Ø 0.26") 3 X Ø 3.2 mm 3 X Ø 3.2 mm R 7.6 mm (Ø 0.26") R 7.6 mm (Ø 0.26") (R 0.30) (R 0.30) 5.0 mm 5.0 mm 4.8 mm4.8 mm CL (0.20")(0.20") (0.19")(0.19") 4.5 mm 4.5 mm(0.18") (0.18") 16.5 mm 3.7 mm 6.8 mm (0.65")10.5 mm (0.15") (0.27") (0.41") 10.5 mm 8.3 mm 8.3 mm (0.42") (0.33") (0.33") 15.0 mm R 15 mm (0.59") 34.2 mm (R 0.59) (1.35") 34.2 mmØ 3.2 mm 29.0 mm 14.0 mm (1.35")(Ø 0.26") (1.14") 0.9 mm (0.55") (0.04")0.9 mm (0.04") 2 X 2.3 mm Ø 3.3 mm(Ø 0.13") (0.09") 10° 16.5 mm (0.65") 20° P/N 119223 rev. G Banner Engineering Corp. - Minneapolis, MN USA - www.bannerengineering.com 9 Tel: 763.544.3164 119223 Apertures Opposed-mode Q12 sensors (standard models only) may be fitted with apertures to narrow or shape the sensor’s effective beam to more closely match the size or profile of the objects being sensed. A common example is the use of “line” (or “slot”) type apertures to sense thread. NOTE: The use of apertures will reduce the sensing range (see table below). Reduced Sensor Range Model Description (Two Apertures Used) APQ12-.5 Circular hole 0.5 mm (0.02") diameter – 10 each 60 mm (2.4") APQ12-1 1 mm (0.04") diameter – 10 each 190 mm (7.5") APQ12-1.5 1.5 mm (0.06") diameter – 10 each 400 mm (15.7") APQ12-2 2 mm (0.08") diameter – 10 each 725 mm (28.5") APQ12-.5H Horizontal slot 0.5 mm (0.02") – 10 each 350 mm (13.8") APQ12-1H 1 mm (0.04") – 10 each 725 mm (28.5") APQ12-.5V Vertical slot 0.5 mm (0.02") – 10 each 450 mm (17.7") APQ12-1V 1 mm (0.04") – 10 each 900 mm (35.4") Protective jacket APQ12-4S 4 mm (0.16") square – 10 each 2000 mm (78.7") APKQ12 Kit containing two of each aperture above – 18 total — WARNING . . . Not To Be Used for Personnel Protection Never use this product as a sensing device for personnel protection. Doing so could lead to serious injury or death This product does NOT include the self-checking redundant circuitry necessary to allow its use in personnel safety applications. A sensor failure or malfunction can cause either an energized or denergized sensor output condition. Consult your Banner Safety Products catalog for safety products that meet OSHA, ANSI and IEC standards for personnel protection. Warranty: Banner Engineering Corp. will repair or replace, free of charge, any product of its manufacture found to be defective at the time it is returned to the factory during the warranty period.This warranty does not cover damage or liability for the improper application of Banner products. This warranty is in lieu of any other warranty either expressed or implied. L 390/24 EN Official Journal of the European Union 31.12.2004 DIRECTIVE 2004/108/EC OF THE EUROPEAN PARLIAMENT AND OF THE COUNCIL of 15 December 2004 on the approximation of the laws of the Member States relating to electromagnetic compatibility and repealing Directive 89/336/EEC (Text with EEA relevance) THE EUROPEAN PARLIAMENT AND THE COUNCIL OF THE EURO- (5) The electromagnetic compatibility of equipment should PEAN UNION, be regulated with a view to ensuring the functioning of the internal market, that is to say, of an area without internal frontiers in which the free movement of goods, Having regard to the Treaty establishing the European Com- persons, services and capital is assured. munity, and in particular Article 95 thereof, Having regard to the proposal from the Commission, (6) The equipment covered by this Directive should include both apparatus and fixed installations. However, separate provision should be made for each. This is so because, Having regard to the opinion of the European Economic and whereas apparatus as such may move freely within the Social Committee (1), Community, fixed installations on the other hand are installed for permanent use at a predefined location, as assemblies of various types of apparatus and, where Acting in accordance with the procedure referred to in Article appropriate, other devices. The composition and func- 251 of the Treaty (2), tion of such installations correspond in most cases to the particular needs of their operators. Whereas: (7) Radio equipment and telecommunications terminal (1) Council Directive 89/336/EEC of 3 May 1989 on the equipment should not be covered by this Directive since approximation of laws of the Member States relating to they are already regulated by Directive 1999/5/EC of the electromagnetic compatibility (3) has been the subject of European Parliament and of the Council of 9 March a review under the initiative known as Simpler Legisla- 1999 on radio equipment and telecommunications term- tion for the Internal Market (SLIM). Both the SLIM inal equipment and the mutual recognition of their4 process and a subsequent in-depth consultation have conformity ( ). The electromagnetic compatibility revealed the need to complete, reinforce and clarify the requirements in both Directives achieve the same level framework established by Directive 89/336/EEC. of protection. (2) Member States are responsible for ensuring that radio- (8) Aircraft or equipment intended to be fitted into aircraft communications, including radio broadcast reception should not be covered by this Directive, since they are and the amateur radio service operating in accordance already subject to special Community or international with International Telecommunication Union (ITU) radio rules governing electromagnetic compatibility. regulations, electrical supply networks and telecommuni- cations networks, as well as equipment connected thereto, are protected against electromagnetic distur- bance. (9) This Directive need not regulate equipment which is inherently benign in terms of electromagnetic compat- ibility. (3) Provisions of national law ensuring protection against electromagnetic disturbance should be harmonised in order to guarantee the free movement of electrical and electronic apparatus without lowering justified levels of (10) This Directive should not deal with the safety of equip- protection in the Member States. ment, since that is dealt with by separate Community or national legislation. (4) Protection against electromagnetic disturbance requires obligations to be imposed on the various economic (11) Where this Directive regulates apparatus, it should refer operators. Those obligations should be applied in a fair to finished apparatus commercially available for the first and effective way in order to achieve such protection. time on the Community market. Certain components or sub-assemblies should, under certain conditions, be (1) OJ C 220, 16.9.2003, p. 13. considered to be apparatus if they are made available to (2) Opinion of the European Parliament of 9 March 2004 (not yet the end-user. published in the Official Journal) and Council Decision of 29 November 2004. (3) OJ L 139, 23.5.1989, p. 19. Directive as last amended by Directive (4) OJ L 91, 7.4.1999, p. 10. Directive as amended by Regulation (EC) 93/68/EEC (OJ L 220, 30.8.1993, p. 1). No 1882/2003 (OJ L 284, 31.10.2003, p. 1). 31.12.2004 EN Official Journal of the European Union L 390/25 (12) The principles on which this Directive is based are those requirements of this Directive. Apparatus placed on the set out in the Council Resolution of 7 May 1985 on a market should bear the ‘CE’ marking attesting to compli- new approach to technical harmonization and stan- ance with this Directive. Although conformity assess- dards (1). In accordance with that approach, the design ment should be the responsibility of the manufacturer, and manufacture of equipment is subject to essential without any need to involve an independent conformity requirements in relation to electromagnetic compat- assessment body, manufacturers should be free to use ibility. Those requirements are given technical expression the services of such a body. by harmonised European standards, to be adopted by the various European standardisation bodies, European Committee for Standardisation (CEN), European Committee for Electro-technical Standardisation (16) The conformity assessment obligation should require the (CENELEC) and European Telecommunications Standards manufacturer to perform an electromagnetic compat- Institute (ETSI). CEN, CENELEC and ETSI are recognised ibility assessment of apparatus, based on relevant as the competent institutions in the field of this Directive phenomena, in order to determine whether or not it for the adoption of harmonised standards, which they meets the protection requirements under this Directive. draw up in accordance with the general guidelines for cooperation between themselves and the Commission, and with the procedure laid down in Directive 98/34/EC of the European Parliament and of the Council of 22 June 1998 laying down a procedure for the provision of (17) Where apparatus is capable of taking different configura- information in the field of technical standards and regu- tions, the electromagnetic compatibility assessment lations and of rules on Information Society services (2). should confirm whether the apparatus meets the protec-tion requirements in the configurations foreseeable by the manufacturer as representative of normal use in the intended applications; in such cases it should be suffi- cient to perform an assessment on the basis of the (13) Harmonised standards reflect the generally acknowl- configuration most likely to cause maximum disturbance edged state of the art as regards electromagnetic compat- and the configuration most susceptible to disturbance. ibility matters in the European Union. It is thus in the interest of the functioning of the internal market to have standards for the electromagnetic compatibility of equip- ment which have been harmonised at Community level. (18) Fixed installations, including large machines and Once the reference to such a standard has been networks, may generate electromagnetic disturbance, or published in the Official Journal of the European Union, be affected by it. There may be an interface between compliance with it should raise a presumption of fixed installations and apparatus, and the electromag- conformity with the relevant essential requirements, netic disturbances produced by fixed installations may although other means of demonstrating such conformity affect apparatus, and vice versa. In terms of electromag- should be permitted. Compliance with a harmonised netic compatibility, it is irrelevant whether the electro- standard means conformity with its provisions and magnetic disturbance is produced by apparatus or by a demonstration thereof by the methods the harmonised fixed installation. Accordingly, fixed installations and standard describes or refers to. apparatus should be subject to a coherent and compre- hensive regime of essential requirements. It should be possible to use harmonised standards for fixed installa- tions in order to demonstrate conformity with the essen- (14) Manufacturers of equipment intended to be connected to tial requirements covered by such standards. networks should construct such equipment in a way that prevents networks from suffering unacceptable degrada- tion of service when used under normal operating condi- tions. Network operators should construct their (19) Due to their specific characteristics, fixed installations networks in such a way that manufacturers of equip- need not be subject to the affixation of the ‘CE’ marking ment liable to be connected to networks do not suffer a or to the declaration of conformity. disproportionate burden in order to prevent networks from suffering an unacceptable degradation of service. The European standardisation organisations should take due account of that objective (including the cumulative (20) It is not pertinent to carry out the conformity assessment effects of the relevant types of electromagnetic of apparatus placed on the market for incorporation into phenomena) when developing harmonised standards. a given fixed installation, and otherwise not commer- cially available, in isolation from the fixed installation into which it is to be incorporated. Such apparatus should therefore be exempted from the conformity (15) It should be possible to place apparatus on the market assessment procedures normally applicable to apparatus. or put it into service only if the manufacturers However, such apparatus should not be permitted to concerned have established that such apparatus has been compromise the conformity of the fixed installation into designed and manufactured in conformity with the which it is incorporated. Should apparatus be incorpo- rated into more than one identical fixed installation, (1) OJ C 136, 4.6.1985, p. 1. identifying the electromagnetic compatibility characteris- (2) OJ L 204, 21.7.1998, p. 37. Directive as last amended by the 2003 tics of these installations should be sufficient to ensure Act of Accession. exemption from the conformity assessment procedure. L 390/26 EN Official Journal of the European Union 31.12.2004 (21) A transitional period is necessary in order to ensure that (c) radio equipment used by radio amateurs within the manufacturers and other concerned parties are able to meaning of the Radio Regulations adopted in the frame- adapt to the new regulatory regime. work of the Constitution and Convention of the ITU (2), unless the equipment is available commercially. Kits of components to be assembled by radio amateurs and (22) Since the objective of this Directive, namely to ensure commercial equipment modified by and for the use of the functioning of the internal market by requiring radio amateurs are not regarded as commercially available equipment to comply with an adequate level of electro- equipment. magnetic compatibility, cannot be sufficiently achieved by Member States and can therefore, by reason of its 3. This Directive shall not apply to equipment the inherent scale and effects, be better achieved at Community level, nature of the physical characteristics of which is such that: the Community may adopt measures, in accordance with the principle of subsidiarity as set out in Article 5 (a) it is incapable of generating or contributing to electromag- of the Treaty. In accordance with the principle of netic emissions which exceed a level allowing radio and proportionality, as set out in that Article, this Directive telecommunication equipment and other equipment to does not go beyond what is necessary in order to operate as intended; and achieve that objective. (b) it will operate without unacceptable degradation in the presence of the electromagnetic disturbance normally consequent upon its intended use. (23) Directive 89/336/EEC should therefore be repealed, 4. Where, for the equipment referred to in paragraph 1, the essential requirements referred to in Annex I are wholly or partly laid down more specifically by other Community direc- tives, this Directive shall not apply, or shall cease to apply, to that equipment in respect of such requirements from the date of implementation of those directives. HAVE ADOPTED THIS DIRECTIVE: 5. This Directive shall not affect the application of Com- munity or national legislation regulating the safety of equip- ment. CHAPTER I Article 2 GENERAL PROVISIONS Definitions 1. For the purposes of this Directive, the following defini- tions shall apply: Article 1 (a) ‘equipment’ means any apparatus or fixed installation; (b) ‘apparatus’ means any finished appliance or combination thereof made commercially available as a single functional Subject matter and scope unit, intended for the end user and liable to generate elec- tromagnetic disturbance, or the performance of which is liable to be affected by such disturbance; 1. This Directive regulates the electromagnetic compatibility of equipment. It aims to ensure the functioning of the internal (c) ‘fixed installation’ means a particular combination of market by requiring equipment to comply with an adequate several types of apparatus and, where applicable, other level of electromagnetic compatibility. This Directive applies to devices, which are assembled, installed and intended to be equipment as defined in Article 2. used permanently at a predefined location; (d) ‘electromagnetic compatibility’ means the ability of equip- 2. This Directive shall not apply to: ment to function satisfactorily in its electromagnetic envir-onment without introducing intolerable electromagnetic disturbances to other equipment in that environment; (a) equipment covered by Directive 1999/5/EC; (e) ‘electromagnetic disturbance’ means any electromagnetic phenomenon which may degrade the performance of (b) aeronautical products, parts and appliances as referred to in equipment. An electromagnetic disturbance may be electro- Regulation (EC) No 1592/2002 of the European Parliament magnetic noise, an unwanted signal or a change in the and of the Council of 15 July 2002 on common rules in propagation medium itself; the field of civil aviation and establishing a European Avia- tion Safety Agency (1); (2) Constitution and Convention of the International Telecommunica- tion Union adopted by the Additional Plenipotentiary Conference (1) OJ L 240, 7.9.2002, p. 1. Regulation as amended by Commission (Geneva, 1992) as amended by the Plenipotentiary Conference Regulation (EC) No 1701/2003 (OJ L 243, 27.9.2003, p. 5). (Kyoto, 1994). 31.12.2004 EN Official Journal of the European Union L 390/27 (f) ‘immunity’ means the ability of equipment to perform as 3. Member States shall not create any obstacles to the intended without degradation in the presence of an electro- display and/or demonstration at trade fairs, exhibitions or magnetic disturbance; similar events of equipment which does not comply with this Directive, provided that a visible sign clearly indicates that such (g) ‘safety purposes’ means the purposes of safeguarding equipment may not be placed on the market and/or put into human life or property; service until it has been brought into conformity with this Directive. Demonstration may only take place provided that (h) ‘electromagnetic environment’ means all electromagnetic adequate measures are taken to avoid electromagnetic distur- phenomena observable in a given location. bances. 2. For the purposes of this Directive the following shall be deemed to be an apparatus within the meaning of paragraph 1(b): Article 5 (a) ‘components’ or ‘sub-assemblies’ intended for incorporation into an apparatus by the end user, which are liable to Essential requirements generate electromagnetic disturbance, or the performance of which is liable to be affected by such disturbance; The equipment referred to in Article 1 shall meet the essential requirements set out in Annex I. (b) ‘mobile installations’ defined as a combination of apparatus and, where applicable, other devices, intended to be moved and operated in a range of locations. Article 6 Article 3 Harmonised standards Placing on the market and/or putting into service 1. ‘Harmonised standard’ means a technical specification adopted by a recognised European standardisation body under Member States shall take all appropriate measures to ensure a mandate from the Commission in conformity with the proce- that equipment is placed on the market and/or put into service dures laid down in Directive 98/34/EC for the purpose of only if it complies with the requirements of this Directive when establishing a European requirement. Compliance with a properly installed, maintained and used for its intended ‘harmonised standard’ is not compulsory. purpose. 2. The compliance of equipment with the relevant harmo- nised standards whose references have been published in the Article 4 Official Journal of the European Union shall raise a presumption, on the part of the Member States, of conformity with the essen- tial requirements referred to in Annex I to which such stan- Free movement of equipment dards relate. This presumption of conformity is limited to the scope of the harmonised standard(s) applied and the relevant 1. Member States shall not impede, for reasons relating to essential requirements covered by such harmonised standard(s). electromagnetic compatibility, the placing on the market and/ or the putting into service in their territory of equipment 3. Where a Member State or the Commission considers that which complies with this Directive. a harmonised standard does not entirely satisfy the essential requirements referred to in Annex I, it shall bring the matter 2. The requirements of this Directive shall not prevent the before the Standing Committee set up by Directive 98/34/EC application in any Member State of the following special (hereinafter ‘the Committee’), stating its reasons. The measures concerning the putting into service or use of equip- Committee shall deliver an opinion without delay. ment: 4. Upon receipt of the Committee's opinion, the Commis- (a) measures to overcome an existing or predicted electromag- sion shall take one of the following decisions with regard to netic compatibility problem at a specific site; the references to the harmonised standard concerned: (b) measures taken for safety reasons to protect public telecom- (a) not to publish; munications networks or receiving or transmitting stations when used for safety purposes in well-defined spectrum (b) to publish with restrictions; situations. (c) to maintain the reference in the Official Journal of the Euro- Without prejudice to Directive 98/34/EC, Member States shall pean Union; notify those special measures to the Commission and to the other Member States. (d) to withdraw the reference from the Official Journal of the European Union. The special measures which have been accepted shall be published by the Commission in the Official Journal of the Euro- The Commission shall inform the Member States of its decision pean Union. without delay. L 390/28 EN Official Journal of the European Union 31.12.2004 CHAPTER II 3. The manufacturer shall provide information on any specific precautions that must be taken when the apparatus is APPARATUS assembled, installed, maintained or used, in order to ensure that, when put into service, the apparatus is in conformity with the protection requirements set out in Annex I, point 1. Article 7 4. Apparatus for which compliance with the protection requirements is not ensured in residential areas shall be accom- Conformity assessment procedure for apparatus panied by a clear indication of this restriction of use, where appropriate also on the packaging. Compliance of apparatus with the essential requirements referred to in Annex I shall be demonstrated by means of the procedure described in Annex II (internal production control). 5. The information required to enable apparatus to be used However, at the discretion of the manufacturer or of his in accordance with the intended purpose of the apparatus shall authorised representative in the Community, the procedure be contained in the instructions accompanying the apparatus. described in Annex III may also be followed. Article 8 Article 10 ‘CE’ marking Safeguards 1. Apparatus whose compliance with this Directive has been established by means of the procedure laid down in Article 7 1. Where a Member State ascertains that apparatus bearing shall bear the ‘CE’ marking which attests to that fact. The the ‘CE’ marking does not comply with the requirements of this affixing of the ‘CE’ marking shall be the responsibility of the Directive, it shall take all appropriate measures to withdraw the manufacturer or his authorised representative in the Com- apparatus from the market, to prohibit its placing on the munity. The ‘CE’ marking shall be affixed in accordance with market or its putting into service, or to restrict the free move- Annex V. ment thereof. 2. Member States shall take the necessary measures to 2. The Member State concerned shall immediately inform prohibit the affixing to the apparatus, or to its packaging, or to the Commission and the other Member States of any such the instructions for its use, of marks which are likely to mislead measure, indicating the reasons and specifying, in particular, third parties in relation to the meaning and/or graphic form of whether non-compliance is due to: the ‘CE’ marking. (a) failure to satisfy the essential requirements referred to in 3. Any other mark may be affixed to the apparatus, its Annex I, where the apparatus does not comply with the packaging, or the instructions for its use, provided that neither harmonised standards referred to in Article 6; the visibility nor the legibility of the ‘CE’ marking is thereby impaired. (b) incorrect application of the harmonised standards referred to in Article 6; 4. Without prejudice to Article 10, if a competent authority establishes that the ‘CE’ marking has been unduly affixed, the (c) shortcomings in the harmonised standards referred to in manufacturer or his authorised representative in the Com- Article 6. munity shall bring the apparatus into conformity with the provisions concerning the ‘CE’ marking under conditions 3. The Commission shall consult the parties concerned as imposed by the Member State concerned. soon as possible, following which it shall inform the Member States whether or not it finds the measure to be justified. Article 9 4. Where the measure referred to in paragraph 1 is attrib- uted to a shortcoming in harmonised standards, the Commis- Other marks and information sion, after consulting the parties, shall, if the Member State concerned intends to uphold the measure, bring the matter 1. Each apparatus shall be identified in terms of type, batch, before the Committee and initiate the procedure laid down in serial number or any other information allowing for the identi- Article 6(3) and (4). fication of the apparatus. 5. Where the non-compliant apparatus has been subject to 2. Each apparatus shall be accompanied by the name and the conformity assessment procedure referred to in Annex III, address of the manufacturer and, if he is not established within the Member State concerned shall take appropriate action in the Community, the name and address of his authorised repre- respect of the author of the statement referred to in Annex III, sentative or of the person in the Community responsible for point 3, and shall inform the Commission and the other placing the apparatus on the Community market. Member States accordingly. 31.12.2004 EN Official Journal of the European Union L 390/29 Article 11 CHAPTER III Decisions to withdraw, prohibit or restrict the free move- FIXED INSTALLATIONS ment of apparatus 1. Any decision taken pursuant to this Directive to withdraw Article 13 apparatus from the market, prohibit or restrict its placing on the market or its putting into service, or restrict the free move- ment thereof, shall state the exact grounds on which it is based. Fixed installations Such decisions shall be notified without delay to the party concerned, who shall at the same time be informed of the 1. Apparatus which has been placed on the market and remedies available to him under the national law in force in which may be incorporated into a fixed installation is subject the Member State in question and of the time limits to which to all relevant provisions for apparatus set out in this Directive. such remedies are subject. However, the provisions of Articles 5, 7, 8 and 9 shall not be 2. In the event of a decision as referred to in paragraph 1, compulsory in the case of apparatus which is intended for the manufacturer, his authorised representative, or any other incorporation into a given fixed installation and is otherwise interested party shall have the opportunity to put forward his not commercially available. In such cases, the accompanying point of view in advance, unless such consultation is not documentation shall identify the fixed installation and its elec- possible because of the urgency of the measure to be taken as tromagnetic compatibility characteristics and shall indicate the justified in particular with respect to public interest require- precautions to be taken for the incorporation of the apparatus ments. into the fixed installation in order not to compromise the conformity of that installation. It shall furthermore include the information referred to in Article 9(1) and (2). 2. Where there are indications of non-compliance of the Article 12 fixed installation, in particular, where there are complaints about disturbances being generated by the installation, the competent authorities of the Member State concerned may Notified bodies request evidence of compliance of the fixed installation, and, when appropriate, initiate an assessment. 1. Member States shall notify the Commission of the bodies which they have designated to carry out the tasks referred to in Where non-compliance is established, the competent authori- Annex III. When determining the bodies to be designated, ties may impose appropriate measures to bring the fixed instal- Member States shall apply the criteria laid down in Annex VI. lation into compliance with the protection requirements set out in Annex I, point 1. Such notification shall state whether the bodies are designated to carry out the tasks referred to in Annex III for all apparatus 3. Member States shall set out the necessary provisions for covered by this Directive, and/or the essential requirements identifying the person or persons responsible for the establish- referred to in Annex I or whether the scope of designation is ment of compliance of a fixed installation with the relevant limited to certain specific aspects and/or categories of appa- essential requirements. ratus. 2. Bodies which comply with the assessment criteria estab- CHAPTER IV lished by the relevant harmonised standards shall be presumed to comply with the criteria set out in Annex VI covered by such harmonised standards. The Commission shall publish in FINAL PROVISIONS the Official Journal of the European Union the references of those standards. Article 14 3. The Commission shall publish in the Official Journal of the European Union a list of notified bodies. The Commission shall ensure that the list is kept up to date. Repeal Directive 89/336/EEC is hereby repealed as from 20 July 2007. 4. If a Member State finds that a notified body no longer meets the criteria listed in Annex VI, it shall inform the Commission and the other Member States accordingly. The References to Directive 89/336/EEC shall be construed as refer- Commission shall withdraw the reference to that body from ences to this Directive and should be read in accordance with the list referred to in paragraph 3. the correlation table set out in Annex VII. L 390/30 EN Official Journal of the European Union 31.12.2004 Article 15 Article 17 Transitional provisions Entry into force Member States shall not impede the placing on the market and/ or the putting into service of equipment which is in compli- This Directive shall enter into force on the twentieth day after ance with the provisions of Directive 89/336/EEC and which its publication in the Official Journal of the European Union. was placed on the market before 20 July 2009. Article 16 Article 18 Transposition Addressees 1. Member States shall adopt and publish the laws, regula- tions and administrative provisions necessary to comply with This Directive is addressed to the Member States. this Directive by 20 January 2007. They shall forthwith inform the Commission thereof. They shall apply those provisions as from 20 July 2007. When Member States adopt those provi- sions, they shall contain a reference to this Directive or shall be accompanied by such reference on the occasion of their official Done at Strasbourg, 15 December 2004. publication. The methods of making such reference shall be laid down by Member States. For the European Parliament For the Council 2. Member States shall communicate to the Commission the texts of the provisions of national law which they adopt in the The President The President field covered by this Directive. J. BORRELL FONTELLES A. NICOLAÏ 31.12.2004 EN Official Journal of the European Union L 390/31 ANNEX I ESSENTIAL REQUIREMENTS REFERRED TO IN ARTICLE 5 1. Protection requirements Equipment shall be so designed and manufactured, having regard to the state of the art, as to ensure that: (a) the electromagnetic disturbance generated does not exceed the level above which radio and telecommunications equipment or other equipment cannot operate as intended; (b) it has a level of immunity to the electromagnetic disturbance to be expected in its intended use which allows it to operate without unacceptable degradation of its intended use. 2. Specific requirements for fixed installations Installation and intended use of components A fixed installation shall be installed applying good engineering practices and respecting the information on the intended use of its components, with a view to meeting the protection requirements set out in Point 1. Those good engineering practices shall be documented and the documentation shall be held by the person(s) responsible at the disposal of the relevant national authorities for inspection purposes for as long as the fixed installation is in opera- tion. L 390/32 EN Official Journal of the European Union 31.12.2004 ANNEX II CONFORMITY ASSESSMENT PROCEDURE REFERRED TO IN ARTICLE 7 (internal production control) 1. The manufacturer shall perform an electromagnetic compatibility assessment of the apparatus, on the basis of the relevant phenomena, with a view to meeting the protection requirements set out in Annex I, point 1. The correct application of all the relevant harmonised standards whose references have been published in the Official Journal of the European Union shall be equivalent to the carrying out of the electromagnetic compatibility assessment. 2. The electromagnetic compatibility assessment shall take into account all normal intended operating conditions. Where the apparatus is capable of taking different configurations, the electromagnetic compatibility assessment shall confirm whether the apparatus meets the protection requirements set out in Annex I, point 1, in all the possible configurations identified by the manufacturer as representative of its intended use. 3. In accordance with the provisions set out in Annex IV, the manufacturer shall draw up technical documentation providing evidence of the conformity of the apparatus with the essential requirements of this Directive. 4. The manufacturer or his authorised representative in the Community shall hold the technical documentation at the disposal of the competent authorities for at least ten years after the date on which such apparatus was last manufac- tured. 5. The compliance of apparatus with all relevant essential requirements shall be attested by an EC declaration of confor- mity issued by the manufacturer or his authorised representative in the Community. 6. The manufacturer or his authorised representative in the Community shall hold the EC declaration of conformity at the disposal of the competent authorities for a period of at least ten years after the date on which such apparatus was last manufactured. 7. If neither the manufacturer nor his authorised representative is established within the Community, the obligation to hold the EC declaration of conformity and the technical documentation at the disposal of the competent authorities shall lie with the person who places the apparatus on the Community market. 8. The manufacturer must take all measures necessary to ensure that the products are manufactured in accordance with the technical documentation referred to in point 3 and with the provisions of this Directive that apply to them. 9. The technical documentation and the EC declaration of conformity shall be drawn up in accordance with the provi- sions set out in Annex IV. 31.12.2004 EN Official Journal of the European Union L 390/33 ANNEX III CONFORMITY ASSESSMENT PROCEDURE REFERRED TO IN ARTICLE 7 1. This procedure consists of applying Annex II, completed as follows: 2. The manufacturer or his authorised representative in the Community shall present the technical documentation to the notified body referred to in Article 12 and request the notified body for an assessment thereof. The manufacturer or his authorised representative in the Community shall specify to the notified body which aspects of the essential requirements must be assessed by the notified body. 3. The notified body shall review the technical documentation and assess whether the technical documentation properly demonstrates that the requirements of the Directive that it is to assess have been met. If the compliance of the appa- ratus is confirmed, the notified body shall issue a statement to the manufacturer or his authorised representative in the Community confirming the compliance of the apparatus. That statement shall be limited to those aspects of the essential requirements which have been assessed by the notified body. 4. The manufacturer shall add the statement of the notified body to the technical documentation. L 390/34 EN Official Journal of the European Union 31.12.2004 ANNEX IV TECHNICAL DOCUMENTATION AND EC DECLARATION OF CONFORMITY 1. Technical documentation The technical documentation must enable the conformity of the apparatus with the essential requirements to be assessed. It must cover the design and manufacture of the apparatus, in particular: — a general description of the apparatus; — evidence of compliance with the harmonised standards, if any, applied in full or in part; — where the manufacturer has not applied harmonised standards, or has applied them only in part, a description and explanation of the steps taken to meet the essential requirements of the Directive, including a description of the electromagnetic compatibility assessment set out in Annex II, point 1, results of design calculations made, examinations carried out, test reports, etc.; — a statement from the notified body, when the procedure referred to in Annex III has been followed. 2. EC declaration of conformity The EC declaration of conformity must contain, at least, the following: — a reference to this Directive, — an identification of the apparatus to which it refers, as set out in Article 9(1), — the name and address of the manufacturer and, where applicable, the name and address of his authorised repre- sentative in the Community, — a dated reference to the specifications under which conformity is declared to ensure the conformity of the appa- ratus with the provisions of this Directive, — the date of that declaration, — the identity and signature of the person empowered to bind the manufacturer or his authorised representative. 31.12.2004 EN Official Journal of the European Union L 390/35 ANNEX V ‘CE’ MARKING REFERRED TO IN ARTICLE 8 The ‘CE’ marking shall consist in the initials ‘CE’ taking the following form: The ‘CE’ marking must have a height of at least 5 mm. If the ‘CE’ marking is reduced or enlarged the proportions given in the above graduated drawing must be respected. The ‘CE’ marking must be affixed to the apparatus or to its data plate. Where this is not possible or not warranted on account of the nature of the apparatus, it must be affixed to the packaging, if any, and to the accompanying documents. Where the apparatus is the subject of other Directives covering other aspects and which also provide for the ‘CE’ marking, the latter shall indicate that the apparatus also conforms with those other Directives. However, where one or more of those Directives allow the manufacturer, during a transitional period, to choose which arrangements to apply, the ‘CE’ marking shall indicate conformity only with the Directives applied by the manufacturer. In that case, particulars of the Directives applied, as published in the Official Journal of the European Union, must be given in the documents, notices or instructions required by the Directives and accompanying such apparatus. L 390/36 EN Official Journal of the European Union 31.12.2004 ANNEX VI CRITERIA FOR THE ASSESSMENT OF THE BODIES TO BE NOTIFIED 1. The bodies notified by the Member States shall fulfil the following minimum conditions: (a) availability of personnel and of the necessary means and equipment; (b) technical competence and professional integrity of personnel; (c) independence in preparing the reports and performing the verification function provided for in this Directive; (d) independence of staff and technical personnel in relation to all interested parties, groups or persons directly or indirectly concerned with the equipment in question; (e) maintenance of professional secrecy by personnel; (f) possession of civil liability insurance unless such liability is covered by the Member State under national law. 2. Fulfilment of the conditions laid down in point 1 shall be verified at intervals by the competent authorities of the Member State. 31.12.2004 EN Official Journal of the European Union L 390/37 ANNEX VII CORRELATION TABLE Directive 89/336/EEC This Directive Article 1, point 1 Article 2(1)(a), (b) and (c) Article 1, point 2 Article 2(1)(e) Article 1, point 3 Article 2(1)(f) Article 1, point 4 Article 2(1)(d) Article 1, points 5 and 6 - Article 2(1) Article 1(1) Article 2(2) Article 1(4) Article 2(3) Article 1(2) Article 3 Article 3 Article 4 Article 5 and Annex I Article 5 Article 4(1) Article 6 Article 4(2) Article 7(1)(a) Article 6(1) and (2) Article 7(1)(b) - Article 7(2). - Article 7(3) - Article 8(1) Article 6(3) and (4) Article 8(2) - Article 9(1) Article 10(1) and (2) Article 9(2) Article 10(3) and (4) Article 9(3) Article 10(5) Article 9(4) Article 10(3) Article 10(1), first sub-paragraph Article 7, Annexes II and III Article 10(1), second sub-paragraph Article 8 Article 10(2) Article 7, Annexes II and III Article 10(3) - Article 10(4) - Article 10(5) Article 7, Annexes II and III Article 10(6) Article 12 Article 11 Article 14 Article 12 Article 16 Article 13 Article 18 Annex I, point 1 Annex IV, point 2 Annex I, point 2 Annex V Annex II Annex VI Annex III, last paragraph Article 9(5) µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 Short-Circuit Protection µA741M . . . J PACKAGE Offset-Voltage Null Capability (TOP VIEW) Large Common-Mode and Differential Voltage Ranges NC 1 14 NC NC 2 13 NC No Frequency Compensation Required OFFSET N1 3 12 NC Low Power Consumption IN– 4 11 VCC+ No Latch-Up IN+ 5 10 OUT Designed to Be Interchangeable With VCC– 6 9 OFFSET N2 Fairchild µA741 NC 7 8 NC description µA741M . . . JG PACKAGE µA741C, µA741I . . . D, P, OR PW PACKAGE The µA741 is a general-purpose operational (TOP VIEW) amplifier featuring offset-voltage null capability. The high common-mode input voltage range and OFFSET N1 1 8 NC the absence of latch-up make the amplifier ideal IN– 2 7 VCC+ for voltage-follower applications. The device is IN+ 3 6 OUT short-circuit protected and the internal frequency VCC– 4 5 OFFSET N2 compensation ensures stability without external components. A low value potentiometer may be µA741M . . . U PACKAGE connected between the offset null inputs to null (TOP VIEW) out the offset voltage as shown in Figure 2. The µA741C is characterized for operation from NC 1 10 NC 0°C to 70°C. The µA741I is characterized for OFFSET N1 2 9 NC operation from –40°C to 85°C.The µA741M is IN– 3 8 VCC+ characterized for operation over the full military IN+ 4 7 OUT temperature range of –55°C to 125°C. VCC– 5 6 OFFSET N2 symbol µA741M . . . FK PACKAGE OFFSET N1 (TOP VIEW) IN + + OUT IN – – OFFSET N2 3 2 1 20 19 NC 4 18 NC IN– 5 17 VCC+ NC 6 16 NC IN+ 7 15 OUT NC 8 14 NC 9 10 11 12 13 NC – No internal connection PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 NC NC VC C – OFFSET N1 NC NC OFFSET N2 NC NC NC µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 AVAILABLE OPTIONS PACKAGED DEVICES CHIP T SMALL CHIP CERAMIC CERAMIC PLASTIC FLATA TSSOP FORMOUTLINE CARRIER DIP DIP DIP PACK (PW) (Y) (D) (FK) (J) (JG) (P) (U) 0°C to 70°C µA741CD µA741CP µA741CPW µA741Y –40°C to 85°C µA741ID µA741IP –55°C to 125°C µA741MFK µA741MJ µA741MJG µA741MU The D package is available taped and reeled. Add the suffix R (e.g., µA741CDR). schematic VCC+ IN– OUT IN+ OFFSET N1 OFFSET N2 VCC– Component Count Transistors 22 Resistors 11 Diode 1 Capacitor 1 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 µA741Y chip information This chip, when properly assembled, displays characteristics similar to the µA741C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS VCC+ (7) (7) (6) (3) IN+ + (6) (2) OUT IN– – OFFSET N1 (1) (4) (8) OFFSET N2 (5) VCC– 45 (5) (1) CHIP THICKNESS: 15 TYPICAL (4) BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C. (2) (3) TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† µA741C µA741I µA741M UNIT Supply voltage, VCC+ (see Note 1) 18 22 22 V Supply voltage, VCC– (see Note 1) –18 –22 –22 V Differential input voltage, VID (see Note 2) ±15 ±30 ±30 V Input voltage, VI any input (see Notes 1 and 3) ±15 ±15 ±15 V Voltage between offset null (either OFFSET N1 or OFFSET N2) and VCC– ±15 ±0.5 ±0.5 V Duration of output short circuit (see Note 4) unlimited unlimited unlimited Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA 0 to 70 –40 to 85 –55 to 125 °C Storage temperature range –65 to 150 –65 to 150 –65 to 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J, JG, or U package 300 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D, P, or PW package 260 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–. 2. Differential voltages are at IN+ with respect to IN–. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or either power supply. For the µA741M only, the unlimited duration of the short circuit applies at (or below) 125°C case temperature or 75°C free-air temperature. DISSIPATION RATING TABLE TA ≤ 25°C DERATING DERATE TA = 70°C TA = 85°C TA = 125°CPACKAGE POWER RATING FACTOR ABOVE TA POWER RATING POWER RATING POWER RATING D 500 mW 5.8 mW/°C 64°C 464 mW 377 mW N/A FK 500 mW 11.0 mW/°C 105°C 500 mW 500 mW 275 mW J 500 mW 11.0 mW/°C 105°C 500 mW 500 mW 275 mW JG 500 mW 8.4 mW/°C 90°C 500 mW 500 mW 210 mW P 500 mW N/A N/A 500 mW 500 mW N/A PW 525 mW 4.2 mW/°C 25°C 336 mW N/A N/A U 500 mW 5.4 mW/°C 57°C 432 mW 351 mW 135 mW 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted) TEST µA741C µA741I, µA741M PARAMETER T † UNIT CONDITIONS A MIN TYP MAX MIN TYP MAX 25°C 1 6 1 5 VIO Input offset voltage VO = 0 mV Full range 7.5 6 ∆VIO(adj) Offset voltage adjust range VO = 0 25°C ±15 ±15 mV 25°C 20 200 20 200 IIO Input offset current VO = 0 nA Full range 300 500 25°C 80 500 80 500 IIB Input bias current VO = 0 nA Full range 800 1500 Common-mode input 25°C ±12 ±13 ±12 ±13 VICR Vvoltage range Full range ±12 ±12 RL = 10 kΩ 25°C ±12 ±14 ±12 ±14 Maximum peak output RL ≥ 10 kΩ Full range ±12 ±12 VOM Vvoltage swing RL = 2 kΩ 25°C ±10 ±13 ±10 ±13 RL ≥ 2 kΩ Full range ±10 ±10 Large-signal differential RL ≥ 2 kΩ 25°C 20 200 50 200 AVD V/mVvoltage amplification VO = ±10 V Full range 15 25 ri Input resistance 25°C 0.3 2 0.3 2 MΩ ro Output resistance VO = 0, See Note 5 25°C 75 75 Ω Ci Input capacitance 25°C 1.4 1.4 pF Common-mode rejection 25°C 70 90 70 90 CMRR VIC = VICRmin dBratio Full range 70 70 Supply voltage sensitivity 25°C 30 150 30 150 kSVS V(∆V /∆V ) CC = ±9 V to ±15 V µV/V IO CC Full range 150 150 IOS Short-circuit output current 25°C ±25 ±40 ±25 ±40 mA 25°C 1.7 2.8 1.7 2.8 ICC Supply current VO = 0, No load mA Full range 3.3 3.3 25°C 50 85 50 85 PD Total power dissipation VO = 0, No load mW Full range 100 100 † All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for the µA741C is 0°C to 70°C, the µA741I is –40°C to 85°C, and the µA741M is –55°C to 125°C. NOTE 5: This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. operating characteristics, VCC± = ±15 V, TA = 25°C µA741C µA741I, µA741M PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX tr Rise time VI = 20 mV, RL = 2 kΩ, 0.3 0.3 µs Overshoot factor CL = 100 pF, See Figure 1 5% 5% V = 10 V, R = 2 kΩ, SR Slew rate at unity gain I L 0.5 0.5 V/µs CL = 100 pF, See Figure 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 electrical characteristics at specified free-air temperature, VCC± = ±15 V, TA = 25°C (unless otherwise noted) µA741Y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX VIO Input offset voltage VO = 0 1 6 mV ∆VIO(adj) Offset voltage adjust range VO = 0 ±15 mV IIO Input offset current VO = 0 20 200 nA IIB Input bias current VO = 0 80 500 nA VICR Common-mode input voltage range ±12 ±13 V RL = 10 kΩ ±12 ±14 VOM Maximum peak output voltage swing V RL = 2 kΩ ±10 ±13 AVD Large-signal differential voltage amplification RL ≥ 2 kΩ 20 200 V/mV ri Input resistance 0.3 2 MΩ ro Output resistance VO = 0, See Note 5 75 Ω Ci Input capacitance 1.4 pF CMRR Common-mode rejection ratio VIC = VICRmin 70 90 dB kSVS Supply voltage sensitivity (∆VIO/∆VCC) VCC = ±9 V to ±15 V 30 150 µV/V IOS Short-circuit output current ±25 ±40 mA ICC Supply current VO = 0, No load 1.7 2.8 mA PD Total power dissipation VO = 0, No load 50 85 mW † All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. NOTE 5: This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. operating characteristics, VCC± = ±15 V, TA = 25°C µA741Y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX tr Rise time VI = 20 mV, RL = 2 kΩ, 0.3 µs Overshoot factor CL = 100 pF, See Figure 1 5% V = 10 V, R = 2 kΩ, SR Slew rate at unity gain I L 0.5 V/µs CL = 100 pF, See Figure 1 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 PARAMETER MEASUREMENT INFORMATION VI – OUT IN + 0 V INPUT VOLTAGE WAVEFDORM CL = 100 pF RL = 2 kΩ TEST CIRCUIT Figure 1. Rise Time, Overshoot, and Slew Rate APPLICATION INFORMATION Figure 2 shows a diagram for an input offset voltage null circuit. IN+ + OUT IN– – OFFSET N2 OFFSET N1 10 kΩ To VCC– Figure 2. Input Offset Voltage Null Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 TYPICAL CHARACTERISTICS† INPUT OFFSET CURRENT INPUT BIAS CURRENT vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 100 400 ÏÏÏÏÏ VCC+ = 15 V V 90 V = –15 V CC+ = 15 V ÏÏCCÏ– ÏÏ 350ÏVÏÏ = –ÏÏCC– 15 V 80ÏÏÏÏÏ ÏÏÏÏÏ 300 70 60 250 50 200 40 150 30 100 20 10 50 0 0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 3 Figure 4 MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE ±14 VCC+ = 15 V ±13 VCC– = –15 V TA = 25°C±12 ±11 ±10 ±9 ±8 ±7 ±6 ±5 ±4 0.1 0.2 0.4 0.7 1 2 4 7 10 RL – Load Resistance – kΩ Figure 5 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I IO – Input Offset Current – nA VOM – Maximum Peak Output Voltage – V I IB – Input Bias Current – nA µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 TYPICAL CHARACTERISTICS OPEN-LOOP SIGNAL DIFFERENTIAL MAXIMUM PEAK OUTPUT VOLTAGE VOLTAGE AMPLIFICATION vs vs FREQUENCY SUPPLY VOLTAGE ±20 400 V = 15 V VO = ±10 VCC+ ±18 V = –15 V RL = 2 kΩCC– R = 10 kΩ TA = 25°CL ±16 200TA = 25°C ±14 100 ±12 ±10 ±8 40 ±6 ±4 20 ±2 0 10 100 1k 10k 100k 1M 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – Hz VCC± – Supply Voltage – V Figure 6 Figure 7 OPEN-LOOP LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREQUENCY 110 100 VCC+ = 15 V V 90 CC– = –15 V VO = ±10 V 80 RL = 2 kΩ TA = 25°C 70 60 50 40 30 20 10 0 –10 1 10 100 1k 10k 100k 1M 10M f – Frequency – Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 VOM – Maximum Peak Output Voltage – V AVD – Open-Loop Signal Differential Voltage Amplification – dB AVD – Open-Loop Signal Differential Voltage Amplification – V/mV µA741, µA741Y GENERAL-PURPOSE OPERATIONAL AMPLIFIERS SLOS094B – NOVEMBER 1970 – REVISED SEPTEMBER 2000 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO OUTPUT VOLTAGE vs vs FREQUENCY ELAPSED TIME 100 28 VCC+ = 15 V 90 VCC– = –15 V 24 BS = 10 kΩ80 TA = 25°C 20 70 90% ÏÏ 60 16 50 12 40 8 30 4 VCC+ = 15 V 20 VCC– = –15 V10% R 0 L = 2 kΩ 10 CL = 100 pF tr TA = 25°C 0 –4 1 100 10k 1M 100M 0 0.5 1 1.5 2 2.5 f – Frequency – Hz t – Time − µs Figure 8 Figure 9 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE 8 VCC+ = 15 V 6 VCC– = –15 V RL = 2 kΩ CL = 100 pF4 TA = 25°C VO 2 0 VI –2 –4 –6 –8 0 10 20 30 40 50 60 70 80 90 t – Time – µs Figure 10 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CMRR – Common-Mode Rejection Ratio – dB Input and Output Voltage – V VO – Output Voltage – mV IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  2000, Texas Instruments Incorporated This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components. Detalles de Producto USB al adaptador RS232 (ZT-RS232B) USB al adaptador RS232 (ZT-RS232B) Descripción de Producto Características: 1. Convertir el puerto estándar del USB a la conformidad de la interfaz en serie 2. de RS-232 DB9 completamente con la especificación 2.0, 1.1 del USB 3. Compatible a los equipos con RS-232 la ayuda estándar de la interfaz en serie 4. sobre tarifa de transferencia de datos 1Mbps 5. Modo automático del apretón de manos de Suport 6. Gerencia para despertar de la ayuda y de la energía alejada 7. Windows 98 /98SE/ME/2000/XP/Vista y 8. máximos X de la ayuda o sobre la comunicación de la velocidad completa del USB 8. y energías bajas accionadas autobús consume Contenido del paquete: USB del A. al cable RS232 Cable de extensión del USB del B. C. CD del conductor de software Otros artículos opcionales: USB al cable RS232 (DB9 solamente) USB al cable RS232 (DB9 y DB25) Tarjeta de PCMCIA RS232 (DB9) --------------------------------------------------------------------------- El Cable Adaptador USB a Puerto Serie RS232 DB9 de 1 pie de Startech.com permite conectar dispositivos seriales RS232 DB9 a su Mac o PC portátil o de escritorio a través de un puerto USB, como si el ordenador tuviera un conector DB9M incorporado. Una solución eficaz y económica que permite acortar la distancia en términos de compatibilidad entre ordenadores modernos y periféricos preexistentes con conectividad serial. Viene con 2-años de garantía y soporte técnico gratuito de por vida con el respaldo de StarTech.com The StarTech.com Advantage  Instalación y operación simple que brinda conectividad serial a PCs más antiguas.  Al ser alimentado por el bus USB se evitan las molestias de estar acarreando un adaptador de corriente externo para este puerto serie adicional  La larga lista de sistemas operativos compatibles hace de este dispositivo un producto perfecto para casi todas las aplicaciones RS232 Especificaciones Técnicas Garantía Warranty 2 Years Hardware Cantidad de Puertos 1 Estilo de Puerto Cable Adapter Interfaz Serial Tipo de Bus USB 2.0 USB 1.1/2.0 Estándares Industriales RS232 ID del Conjunto de Chips Prolific - PL-2303 Conector(es) Tipo(s) de Conector(es) 1 - DB-9 (9 pin; D-Sub) Macho 1 - USB A (4 pin) Macho Rendimiento Tasa Máxima de Baudios 921.6 Kbps Protocolo Serie RS-232 FIFO 192 Bytes Software Windows® 7 (32/64), Vista(32/64), XP(32/64), 2000, ME, 98SE Compatibilidad OS Windows® Server 2008 R2 Mac OS 10.x (Tested up to 10.8) Linux Características Físicas Longitud del Cable 304.8 mm [12 in] Tipo de Gabinete Plástico Longitud del Producto 370 mm [14.6 in] Ancho del Producto 34 mm [1.3 in] Altura del Producto 18 mm [0.7 in] Peso del Producto 81.6 g [2.9 oz] Requisitos Ambientales Humedad HR 0~65% Temperatura de Almacenamiento -20°C to 80°C (-4°F to 176°F) Temperatura Operativa 0°C to 60°C (32°F to 140°F) Información de la Caja Peso (de la Caja) del Envío 0.1 kg [0.2 lb] 7.1.- Comunicación serie Comentaremos la comunicación SCI (Serial Comunication Interface), poniendo un sencillo ejemplo del funcionamiento y utilidades con el puerto RS-232. Después haremos hincapié en nuestro dispositivo SCI por USB con el integrado de la empresa FTDI, FT232BM, el cual es un transciver capaz de emular un VCP en nuestro ordenador actuando como hardware el puerto USB. 7.1.1 RS-232 SCI es un enlace serie asíncrono que data de 1962. También es conocido como UART (Universal Asynchronous receiver transmitter). Es full-duplex y sólo admite la transmisión-recepción entre dos elementos (punto a punto). La velocidad máxima de transmisión suele ser 256kbps con cables de15m (50 pies). El protocolo es el de la norma RS-232 pero los niveles eléctricos difieren, por lo que es necesario un integrado adaptador de niveles tipo MAX232 para poder utilizar el SCI como puerto RS-232. Dicho puerto es también conocido como puerto COM o puerto serie. 7.1.1.1 Conectores y cables El conector más usual es el DB9, mostrado en la siguiente figura. Conector DB9 y función de cada línea El conector macho (plug) y el hembra (socket) son algo diferentes. En el primero, la patilla 2 corresponde a la línea de recepción, y la 3 a la línea de transmisión. En el segundo ocurre al revés. De este modo, al interconectar dos dispositivos, si uno tiene conector macho y otro hembra, el cable a utilizar será un cable no cruzado. Si los dos dispositivos tienen el mismo tipo de conector entonces será necesario un cable cruzado, en el que el pin 3 de un extremo está conectado al 2 del otro y viceversa. El conector RS-232 de nuestro PC es macho. Dado que los cables más comunes y fáciles de encontrar son los macho-hembra, lo más cómodo es que en nuestra tarjeta utilicemos al menos un conector hembra. A la hora de diseñar la placa tendremos que tener presente: - La patilla 2 y la 3 tienen distintas funciones dependiendo de si el conector es macho o hembra. - Los footprints de los conectores macho y hembra parecen iguales, pero el orden de sus patillas difiere. 7.1.1.2 El integrado MAX232 El integrado MAX232 está basado en dos bombas de carga, una dobladora y otra inversora. Gracias ellas las salidas del integrado pueden tomar valores de +-10V a partir de una tensión de alimentación de 5V. De ahí la necesidad de los condensadores externos, cuyo valor será 1uF para el MAX232 y100nF para el MAX232A y el ST232. Diagrama de conexiones del ST232/MAX232 Cable adaptador TTL-RS232 basado en MAX232 7.1.1.3 Protocolo El estado dominante de la línea es ‘1’, por lo que se dice que es un protocolo NRZ (No Return to Zero). Eléctricamente un ‘1’ se corresponde con un valor entre -3 y -15V, y un ‘0’ con un valor entre +3 y +15V. En primer lugar se manda un bit de start (0) que sirve al receptor para la sincronización. Posteriormente se envía el mensaje (1 byte) y un bit de stop (1). Para enviar el siguiente byte se repetiría el proceso. A este tipo de transmisión se le denomina 8N1. A veces se añade un bit de paridad para comprobar si el dato se ha recibido correctamente. Su valor depende del byte enviado y del tipo de paridad. - Paridad par: Su valor es 0 si el número de ceros enviados es par - Paridad impar: Su valor es 0 si el número de ceros enviados es impar Existen otras variaciones en el protocolo tales como la utilización de dos bits de stop, transmisión de datos de siete bits, etc. por lo que tendremos que verificar que las dos unidades utilizan el mismo protocolo. Nosotros usaremos siempre el 8N1, que es con mucho el más utilizado. Transmisión vía RS232 en modo 7 bits A la hora de visualizar la transmisión con el osciloscopio hay que tener en cuenta dos cosas: - Dado que primero se envía el bit de menos peso, el byte debe ser leído de derecha a izquierda. - Como hemos visto los valores negativos de tensión corresponden a un ‘1’, y los positivos a un ‘0’. Para no liarnos lo mejor es invertir el canal para ver los unos como tensiones positivas y los ceros como tensiones negativas. 7.1.2 USB 7.1.2.1 Introducción al USB El Bus de Serie Universal (USB, de sus siglas en inglés Universal Serial Bus) es una interfaz que provee un estándar de bus serie para conectar dispositivos a un ordenador personal (generalmente a un PC). Un sistema USB tiene un diseño asimétrico, que consiste en un solo servidor y múltiples dispositivos conectados en serie para ampliar la gama de conexión, en una estructura de árbol utilizando concentradores especiales. El estándar incluye la transmisión de energía eléctrica al dispositivo conectado. Algunos dispositivos requieren una potencia mínima, así que se pueden conectar varios sin necesitar fuentes de alimentación extra. La mayoría de los concentradores incluyen fuentes de alimentación que brindan energía a los dispositivos conectados a ellos, pero algunos dispositivos consumen tanta energía que necesitan su propia fuente de alimentación. Los concentradores con fuente de alimentación pueden proporcionarle corriente eléctrica a otros dispositivos sin quitarle corriente al resto de la conexión (dentro de ciertos límites). El diseño del USB tenía en mente eliminar la necesidad de adquirir tarjetas separadas para poner en los puertos bus ISA o PCI, y mejorar las capacidades plug-and-play permitiendo a esos dispositivos ser conectados o desconectados al sistema sin necesidad de reiniciar. Cuando se conecta un nuevo dispositivo, el servidor lo enumera y agrega el software necesario para que pueda funcionar. El USB puede conectar periféricos como ratones, teclados, escáneres, cámaras digitales, impresoras, discos duros, tarjetas de sonido y componentes de red. Para dispositivos multimedia como escáneres y cámaras digitales, el USB se ha convertido en el método estándar de conexión. Para impresoras, el USB ha crecido tanto en popularidad que ha empezado a desplazar a los puertos paralelos porque el USB hace sencillo el poder agregar más de una impresora a un ordenador personal. En el caso de los discos duros, el USB es poco probable que reemplace completamente a los buses como el ATA (IDE) y el SCSI porque el USB tiene un rendimiento un poco más lento que esos otros estándares. El nuevo estándar Serial ATA permite tasas de transferencia de hasta aproximadamente 150 MB por segundo. Sin embargo, el USB tiene una importante ventaja en su habilidad de poder instalar y desinstalar dispositivos sin tener que abrir el sistema, lo cual es útil para dispositivos de almacenamiento desinstalables. Hoy en día, una gran parte de los fabricantes ofrece dispositivos USB portátiles que ofrecen un rendimiento casi indistinguible en comparación con los ATA (IDE). El estándar USB 1.1 tenía dos velocidades de transferencia: 1.5 Mbits/s para teclados, ratón, joysticks, etc., y velocidad completa a 12 Mbit/s. La mayor ventaja del estándar USB 2.0 es añadir un modo de alta velocidad de 480 Mbit/s. En su velocidad más alta, el USB compite directamente con FireWare. Las especificaciones USB 1.0, 1.1 y 2.0 definen dos tipos de conectores para conectar dispositivos al servidor: A y B. Sin embargo, la capa mecánica ha cambiado en algunos conectores. Por ejemplo, el IBM UltraPort es un conector USB privado localizado en la parte superior del LCD de los ordenadores portátiles de IBM. Utiliza un conector mecánico diferente mientras mantiene las señales y protocolos característicos del USB. Otros fabricantes de artículos pequeños han desarrollado también sus medios de conexión pequeños, y una gran variedad de ellos han aparecido. Algunos de baja calidad. Una extensión del USB llamada "USB-On-The-Go" permite a un puerto actuar como servidor o como dispositivo - esto se determina por qué lado del cable está conectado al aparato. Incluso después de que el cable está conectado y las unidades se están comunicando, las 2 unidades pueden "cambiar de papel" bajo el control de un programa. Esta facilidad está específicamente diseñada para dispositivos como PDA, donde el enlace USB podría conectarse a un PC como un dispositivo, y conectarse como servidor a un teclado o ratón. El "USB-On-The-Go" también ha diseñado 2 conectores pequeños, el mini-A y el mini-B, así que esto debería detener la proliferación de conectores miniaturizados de entrada. 7.1.2.2 Conectores y cables El USB dispone en su diversidad diferentes tipos de conectores o clavijas dependiendo del uso que le vayamos a dar. Para ello se dispone en el mercado diferentes tipos de conectores USB, de los cuales sólo indicaremos a continuación aquellos que son los más usados comúnmente. Conector usb Tipo A Conector usb Tipo B Comparativa mini usb macho tipo B y usb macho tipo A Dependiendo del conector, el número de pines difiere entre ellos y también la disposición de las señales, podemos observarlo en la siguiente tabla: Disposición de señales de los distintos conectores usb 7.1.2.3 El integrado FT232BM Dicho integrado realiza las funciones de interface USB <-> Serial mediante hardware, con los mínimos componentes externos. Las principales características del integrado son: El integrado se realiza en smd y tiene 32 patillas, es capaz de soportar Full Handshaking. La UART interna del integrado soporta las siguientes características: - 7 / 8 bits de datos. - 1 / 2 bits de parada. - Y diferentes tipos de fin de datos (paridad, espacio…). La velocidad de la comunicación al ser por hardware es bastante rápida, ésta depende del la señal. - 3M Baudio (TTL). - 1M Baudio (RS232). - 3M Baudios (RS442/RS485). Tiene un buffer de transmisión de 384 bytes y un buffer de transmisión de 128 bytes. Diagrama de pines A continuación pondremos el esquemático realizado en nuestra interface para la comunicación entre el PC y nuestro PIC. Esquemático básico de conexiones usb. Como podemos observar el número de componentes en mínimo, sólo hace falta 4 resistencias y 5 condensadores, de los cuales 4 de ellos son condensadores de desacoplo, usados para limpiar la señal de alimentación que le llega integrado. En esta configuración el integrado se alimenta directamente de la alimentación del USB dado por el PC, con lo que no necesita alimentación externa. También podemos insertar fácilmente una EEPROM externa para poder configurar nuestro dispositivo, de modo que podemos darle un VID y un nombre en concreto a nuestro dispositivo, el cual para nosotros no es muy importante pero si da un gran juego al integrado. Para ello se optó por una EEPROM de la casa Microchip 93C46, sus principales características son: - Memoria EEPROM. - 1K de capacidad de memoria. - 128 x 8 bits de tabla de organización. - Bajo consumo gracias a la tecnología CMOS. Esquemático conexión FT232BM y EEPROM 93C46 El FT232BM tiene dos salidas para mostrar mediante LEDs si éste está recibiendo o enviando información, lo cual nos es tremendamente útil a la hora de hacer pruebas de comunicación y poder ver lo que ocurre a nuestro integrado. Conexión de led para la visualización de transmisión de datos ;************************************************************************************* ;***** Nombre del programa: MEDIDOR DE VOLUMEN ;***** Autor: Juan Diego Jimenez Carpio ;***** Fecha: junio 2013 ;***** Descripción del programa: programa implmentado con algoritmo de multitarea. ;***** controla 4 tareas las cuales tienen las siguiente funciones: ;***** - controlar una pantalla LCD ;***** - escanear un teclado matricial ;***** - realizar caclulos para medir el volumen de cajas ;***** - controlar la transmision de datos por comunicacion USART ;************************************************************************************* .include "C:\VMLAB\include\m16def.inc" .equ distancia_fotos=48;46 ; distancia entre sensores fotoelctricos 46mm .equ rango_maximo_ancho=250 ;250mm .equ rangominimo_ancho=40 ;40mm .equ rango_maximo_alto=250 ;250mm .equ rangominimo_alto=40 ;40mm ; Define here Reset and interrupt vectors, if any ; .dseg .org $240 tecla: .byte 1 exclusive_or: .byte 1 cont_error: .byte 1 flag_inicio_faja: .byte 1 flag_se_a_calibrado: .byte 1 rr22: .byte 1 rr23: .byte 1 flag_mostrar_datos: .byte 1 envia_dat_serial: .byte 1 cantid_cajas: .byte 1 flag_inicio_sensado: .byte 1 datos_nuevos: .byte 1 nueva_velocida: .byte 1 dimensiones_nuevas: .byte 1 cuenta_vel: .byte 1 cuenta_largo: .byte 1 contador: .byte 1 cantidad_datos: .byte 1 flanco_foto1: .byte 1 flanco_foto2: .byte 1 contad_restante_timer2_largo: .byte 1 contad_restante_timer2_vel: .byte 1 vel_0: .byte 1 largo: .byte 1 ancho: .byte 1 alto: .byte 1 ADCaaL:.byte 1 ADCaaH:.byte 1 yadress: .byte 2 adc_anch: .byte 2 adc_alt: .byte 2 .org $60 .cseg reset: rjmp start reti ; Addr $01 rjmp foto1_flanco_subida_bajada ; Addr $02 reti ; Addr $03 rjmp foto2_flanco_subida_bajada ; Addr $04 reti ; Addr $05 reti ; Addr $06 Use 'rjmp myVector' reti ; Addr $07 to define a interrupt vector rjmp fin_cuenta_timer2 ; TIMER2 OVF Timer/Counter2 Overflow ; Addr $08 reti ; Addr $09 reti ; Addr $0A reti ; Addr $0B This is just an example reti ; Addr $0C Not all MCUs have the same reti ; Addr $0D number of interrupt vectors reti ; Addr $0E reti ; Addr $0F reti ; Addr $10 .org $26 rjmp Muestreo_Timer_ADC ;Timer/Counter0 Compare Match .org $30 ; Program starts here after Reset ; start: rjmp IniTareas ;*************************************************************************** ;*** DRIVER MULTITAREA ;*** OPTIMIZADA PARA CONTEXTO ;*** Ventaja: - Guarda todos los registros de trabajo ;*** - No requiere cuidado especial al llamar a DoEvents ;*** - Se puede llamar a DoEvents en cualquier punto ;*** ;*** Desventaja: - Usa mas recusos (RAM): 33 bytes adicionales por cada tarea ;*** - Demora mas tiempo en conmutar tareas: 39+134=173 ;*************************************************************************** .equ NumTareas = 4 .equ TamPila =63 .equ TamPilaContexto= 33 ; 33 adicionales para contexto .cseg Lista_Tareas: .DW Tarea1 .DW Tarea2 .DW Tarea3 .DW Tarea4 .dseg Tarea: .byte 1 ; Current Task: 0-(NumTareas-1) Tabla_SP: .byte 2*NumTareas ; HI-LO Buff_Pila: .byte (TamPila+TamPilaContexto)*NumTareas ; Todas las Pilas de las tareas .cseg IniTareas: cli ; Deshabilito interrupciones ldi R16,high(RAMEND) ; Inicializo Pila out SPH,R16 ldi R16,low(RAMEND) out SPL,R16 rcall IniPorts ; Puertos a estado incial. Reposo ldi ZH,high(Lista_Tareas*2) ldi ZL,low(Lista_Tareas*2) ldi XH,high(Tabla_SP) ldi XL,low(Tabla_SP) ldi YH,high(Buff_Pila-1) ldi YL,low(Buff_Pila-1) ldi R20,NumTareas ; Cantidad de tareas a inicializar IniTareas_Lazo: adiw YL,TamPila ; Me voy al final de la Pila adiw YL,TamPilaContexto out SPH,YH ; Guardo Tarea y contexto out SPL,YL lpm R16,Z+ ; Leo la direccion de inicio de Tarea lpm R17,Z+ push R16 ; Direccion de Tarea push R17 clr R16 ; Inicialmente contexto en $00 ldi R17,33 ; Contexto IniTareas_Contexto: push R16 dec R17 brne IniTareas_Contexto in R0,SPL ; Almaceno en tabla_SP direccion del SP virtual in R1,SPH st X+,R1 st X+,R0 dec R20 brne IniTareas_Lazo ldi R16,0 ; Comienzo en Tarea0 sts Tarea,R16 lds R16,Tabla_SP out SPH,R16 lds R16,Tabla_SP+1 out SPL,R16 sei pop R16 ; Recupero contexto y Run tarea 0 out SREG,R16 pop R31 pop R30 pop R29 pop R28 pop R27 pop R26 pop R25 pop R24 pop R23 pop R22 pop R21 pop R20 pop R19 pop R18 pop R17 pop R16 pop R15 pop R14 pop R13 pop R12 pop R11 pop R10 pop R9 pop R8 pop R7 pop R6 pop R5 pop R4 pop R3 pop R2 pop R1 pop R0 ret ; En caso de no saber el estado inicial de un pin, ; se recomienda ponerlo en PULL-UP IniPorts: push R16 ; ldi R16,$ff ; out PORTB,R16 ldi R16,$00 out DDRB,R16 ; ldi R16,$ff ; out PORTC,R16 ldi R16,$00 out DDRC,R16 ; ldi R16,$ff ; out PORTD,R16 ldi R16,$00 out DDRD,R16 pop R16 ret .macro DoEvents call DoEventos .endm DoEventos: push R0 ; Guarda Contexto push R1 push R2 push R3 push R4 push R5 push R6 push R7 push R8 push R9 push R10 push R11 push R12 push R13 push R14 push R15 push R16 push R17 push R18 push R19 push R20 push R21 push R22 push R23 push R24 push R25 push R26 push R27 push R28 push R29 push R30 push R31 in R16,SREG ; Banderas push R16 ldi XH,high(Tabla_SP) ; Apunto en la tabla_sp al SP actual ldi XL,low(Tabla_SP) lds R16,Tarea lsl R16 add XL,R16 clr R16 adc XH,R16 in R16,SPL ; Leo el SP actual in R17,SPH st X+,R17 ; Almaceno el SP actual st X+,R16 lds R16,Tarea ; Paso a la siguiente Tarea inc R16 cpi R16,NumTareas brne DoEventos_Cont clr R16 ; Regreso a Tarea0 ldi XH,high(Tabla_SP) ldi XL,low(Tabla_SP) DoEventos_Cont: sts Tarea,R16 ld R17,X+ ; Leo SP de la siguiente tarea ld R16,X+ cli out SPH,R17 ; Modifico el SP out SPL,R16 sei nop nop nop nop nop pop R16 ; Recupero contexto out SREG,R16 pop R31 pop R30 pop R29 pop R28 pop R27 pop R26 pop R25 pop R24 pop R23 pop R22 pop R21 pop R20 pop R19 pop R18 pop R17 pop R16 pop R15 pop R14 pop R13 pop R12 pop R11 pop R10 pop R9 pop R8 pop R7 pop R6 pop R5 pop R4 pop R3 pop R2 pop R1 pop R0 ret ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*** TAREA 1 - MENU ;*************************************************************************** .macro printf ldi ZH,high(@1*2) ldi ZL,low(@1*2) ldi r16,@0 ; ubicacion del dato en la pantalla rcall lcd_mensaje .endm Tarea1: ldi R16,0b00111111 ;Puerto B: B0-B3 Nibble de r17s del LCD (lineas de control del LCD): PB5=E PB4=R/W pd7=RS out DDRB,R16 ldi R16,0b10010000 ; PD7 y pd4: TEACH out PORTD,R16 ldi R16,0b11110010 ;Puerto out DDRD,R16 ;PD5:Motor PD2-PD3:Interrupciones externas PD0:RX PD1:TX rcall inicia_variables ;rcall retardo 1 ms rcall Configura_LCD printf $c4,Mensaje_I1 printf $9a,Mensaje_I2 Tarea1_Menu: DoEvents lds r16,tecla cpi r16,$1f ; se presiono menu? brne Tarea1_Menu ldi r16,$0 sts flag_mostrar_datos,r16 Muestra_Menu: rcall Limpiar printf $88,Mensaje_menu printf $c0,Mensaje_menu1 printf $94,Mensaje_menu2 printf $d4,Mensaje_menu3 Escanea_teclado: DoEvents lds r16,tecla cpi r16,$11 ; se presiono 1? brne sensa_2 lds r16,flag_se_a_calibrado cpi r16,10 brsh sise_calibro rcall limpiar printf $c0,debe_calibrar printf $94,debe_calibrar2 rjmp Tarea1_Menu sise_calibro: lds r18,flag_inicio_faja cpi r18,10 brsh faja_prendida ldi zh,high(tabla*2) ;inicia faja a minima velocidad ldi zl,low(tabla*2) lpm r18,z+ lpm r19,z+ out OCR1AH,r19 out OCR1AL,r18 ldi r16,$ff ; la faja a iniciado sts flag_inicio_faja,r16 sts flag_inicio_sensado,r16 faja_prendida: ldi r16,0b11000000 ; int1 int0 out GIFR,r16 ; pone a cero los falgs de interrupciones out GICR,r16 ; abilita interrupciones sei ;abilita interrupciones globales rcall limpiar printf $c0,proceso_iniciado rjmp Tarea1_Menu sensa_2: lds r16,tecla cpi r16,$12 ; se presiono 2? brne sensa_3 rcall limpiar ldi r16,100 sts flag_inicio_faja,r16 printf $c0,Mensaje_variar printf $94,Mensaje_sale lazo_velocida: DoEvents lds r16,tecla cpi r16,$1A ; se presiono up? brne sensa_down ldi r16,0 sts tecla,r16 rcall sube_velocidad rjmp lazo_velocida sensa_down: lds r16,tecla cpi r16,$1B ; se presiono down? brne sensa_menu ldi r16,0 sts tecla,r16 rcall baja_velocidad rjmp lazo_velocida sensa_menu: lds r16,tecla cpi r16,$1F ; se presiono menu? brne lazo_velocida ldi r16,0 sts tecla,r16 rjmp Muestra_Menu sensa_3: lds r16,tecla cpi r16,$13 ; se presiono 3? brne sensa_4 lds r16,flag_inicio_faja cpi r16,10 brsh mensaje_sedebe_detener_faja rcall limpiar printf $80,menu_calibrado printf $c0,calibrado_nuevo printf $94,calibrado_prev printf $d4,calibrado_prev2 lazo_calibrado: DoEvents lds r16,tecla cpi r16,$11 ;se presiono 1? brne sensa_old rcall nueva_calibracion rjmp lazo_calibrado sensa_old: lds r16,tecla cpi r16,$12 ;se presiono 2? brne sensa_meun ldi r16,0 sts tecla,r16 rcall vieja_calibracion rjmp lazo_calibrado sensa_meun: lds r16,tecla cpi r16,$1f ;se preciono menu? brne lazo_calibrado rjmp Muestra_Menu mensaje_sedebe_detener_faja: rcall limpiar printf $c0,debe_detener_faja printf $94,debe_detener_faja2 rjmp Tarea1_Menu sensa_4: lds r16,tecla cpi r16,$14 ; se presiono 4? brne sensa_5 lds r16,flag_inicio_faja cpi r16,10 brlo muestra_mensaje_debeinicarfaja ldi r16,$FF sts flag_mostrar_datos,r16 rcall muestra_etiquetas_dimensiones rjmp Tarea1_Menu muestra_mensaje_debeinicarfaja: rcall limpiar printf $c0,debe_iniciar_faja printf $94,debe_iniciar_faja2 rjmp Tarea1_Menu sensa_5: lds r16,tecla cpi r16,$15 ; se presiono 5? brne sensa_6 rcall limpiar printf $80,msj_serial0 printf $c0,msj_serial1 printf $94,Msj_serial2 lazo_envio_serial: DoEvents lds r16,tecla cpi r16,$11 ; se presiono 1? brne sensa_det_envio ldi r16,$ff sts envia_dat_serial,r16 sts tecla,r16 rcall limpiar printf $c0,envio_data_activo rjmp lazo_envio_serial sensa_det_envio: lds r16,tecla cpi r16,$12 ; se presiono 2? brne sensa_menus ldi r16,0 sts envia_dat_serial,r16 sts tecla,r16 rcall limpiar printf $c0,envio_data_desactivo rjmp lazo_envio_serial sensa_menus: lds r16,tecla cpi r16,$1F ; se presiono menu? brne lazo_envio_serial rjmp Muestra_Menu sensa_6: lds r16,tecla cpi r16,$16 ; se presiono 6? brne sensa_dnuevo ldi r16,0 sts tecla,r16 sts flag_inicio_faja,r16 sts flag_mostrar_datos,r16 sts envia_dat_serial,r16 cli ldi r19,0 out OCR1AH,r19 out OCR1AL,r19 ldi r16,0b11000000 ; int1 int0 out GIFR,r16 ; pone a cero los falgs de interrupciones ldi r16,0b00000000 ; out GICR,r16 ; desabilita interrupciones rcall limpiar printf $c0,stop_proces rjmp Tarea1_Menu sensa_dnuevo: rjmp Escanea_teclado Mensaje_I1: .db "MEDIDOR DE",0,0 Mensaje_I2: .db "VOLUMEN",0 Mensaje_menu: .db "MENU",0,0 Mensaje_menu1: .db "1.Iniciar 2.Vel",0,0 Mensaje_menu2: .db "3.Calibrar 4.Datos",0,0 Mensaje_menu3: .db "5.Envia PC 6.Detener",0,0 Mensaje_variar: .db "Utilice las flechas.",0,0 Mensaje_sale: .db "Menu:Salir",0,0 Mensaje_limite_max: .db "Maximo limite",0 Mensaje_limite_min: .db "Minimo limite",0 espacio: .db " ",0 debe_calibrar: .db "Primero debe",0,0 debe_calibrar2: .db "calibrar sensores",0 proceso_iniciado: .db "Proceso iniciado :)",0 debe_detener_faja: .db "Primero debe parar",0,0 debe_detener_faja2: .db "el proceso",0,0 menu_calibrado: .db "Calibrado",0 calibrado_nuevo: .db "1.Calibrado nuevo",0 calibrado_prev: .db "2.Usar calibrado",0,0 calibrado_prev2: .db " anterior",0,0 colok_caja: .db "Coloque una caja",0,0 colok_caja2: .db "de 21x21x21cm",0 retire_objetos_delafaja: .db "Retire los objetos",0,0 retire_objetos_delafaja2: .db "sobre la faja",0 retire_objetos_delafaja3: .db "luego presione enter",0,0 exito: .db "Sensores calibrados",0 para_salir: .db "Salir: Menu",0 debe_iniciar_faja: .db "Primero debe iniciar",0,0 debe_iniciar_faja2: .db "el proceso",0,0 cajas: .db "Caja",0,0 mensaje_volumen: .db "Volumen:",0,0 cm3: .db "cm",3,0 coma0: .db "0,",0,0 ms: .db "m/s",0 altoo: .db "Alto:",0 cm: .db "cm",0,0 anchoo: .db "Ancho:",0,0 largoo: .db "Largo:",0,0 envio_data_activo: .db "Envio activo",0,0 envio_data_desactivo: .db "Envio desactivado",0 msj_serial0: .db "Envio a PC",0,0 msj_serial1: .db "1.Activar tiemporeal",0,0 msj_serial2: .db "2.Desactivar envio",0,0 stop_proces: .db "Proceso detenido",0,0 ;TABLA VELOCIDADES tabla: ;.dw 4999;11999 19999 .dw 5999;12999 .dw 6999;13999 .dw 7999;14999 .dw 8999;15999 .dw 9998;16999 ;.dw 17999 ; .dw 18999 ;****************************************************************************************************** ***** muestra_etiquetas_dimensiones: push r16 rcall limpiar printf $90,cajas printf $80,mensaje_volumen printf $8c,cm3 printf $e1,coma0 printf $e5,ms printf $94,altoo printf $9d,cm printf $d4,anchoo printf $de,cm printf $c0,largoo printf $ca,cm ldi r16,$D0 rcall WriteIR ldi r16,'#' rcall WriteDR rcall imprime_cajita pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************** imprime_cajita: push r16 push r18 ldi r16,$8f rcall WriteIR ldi r16,4 rcall WriteDR ldi r16,$cf rcall WriteIR ldi r16,4 rcall WriteDR ldi r16,$a3 rcall WriteIR ldi r16,5 rcall WriteDR ldi r16,$a4 rcall WriteIR ldi r16,6 rcall WriteDR ldi r16,$a5 rcall WriteIR ldi r16,6 rcall WriteDR ldi r16,$a6 rcall WriteIR ldi r16,6 rcall WriteDR ldi r16,$a7 rcall WriteIR ldi r16,6 rcall WriteDR ldi r16,$a1 rcall WriteIR ldi r16,6 rcall WriteDR ldi r16,$a2 rcall WriteIR ldi r16,6 rcall WriteDR ldi r16,$a0 rcall WriteIR ldi r16,7 rcall WriteDR ldi r16,$e0 rcall WriteIR ldi r16,4 rcall WriteDR pop r18 pop r16 ret ;****************************************************************************** ;****************************************************************************************************** ***** nueva_calibracion: push r16 rcall limpiar printf $80,colok_caja printf $c0,colok_caja2 printf $94,retire_objetos_delafaja3 lazo_nueva_calibracion: DoEvents lds r16,tecla cpi r16,$1d ;se presiono enter? breq continua_calibrado rjmp lazo_nueva_calibracion continua_calibrado: ldi r16,0 sts tecla,r16 rcall teach_baja_sensor_Pa6_Pa7 ; puerto pa6 y pa7 pasa de alta a baja por 0.05seg rcall limpiar printf $80,retire_objetos_delafaja printf $c0,retire_objetos_delafaja2 printf $94,retire_objetos_delafaja3 lazo_nueva_calibracio: DoEvents lds r16,tecla cpi r16,$1d ; se presiono enter? breq continua_calibrad rjmp lazo_nueva_calibracio continua_calibrad: rcall teach_baja_sensor_Pa6_Pa7 ; puerto pa6 y pa7 pasa de alta a baja por 0.05seg ldi r16,$ff ; flag : ya se calibro sensores sts flag_se_a_calibrado,r16 rcall limpiar printf $c0,exito printf $94,para_salir pop r16 ret ;****************************************************************************************************** ***** teach_baja_sensor_Pa6_Pa7: push r16 cbi porta,6 cbi porta,7 ldi r16,50 rcall RetardoXms sbi porta,6 sbi porta,7 pop r16 ret ;****************************************************************************************************** ***** vieja_calibracion: push r16 ldi r16,$ff ; flag : ya se calibro sensores sts flag_se_a_calibrado,r16 rcall limpiar printf $c0,exito printf $94,para_salir pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** sube_velocidad: push r21 push r22 push r23 in r21,OCR1AL in r21,OCR1AH cpi r21,$27 brsh mostrar_mensaje_limite_max clc ldi zh,high(tabla*2) ldi zl,low(tabla*2) lds r22,rr22 add zl,r22 lds r23,rr23 add zh,r23 lpm r18,z+ lpm r19,z+ out OCR1AH,r19 out OCR1AL,r18 inc r22 inc r22 sts rr22,r22 printf $80,espacio rjmp fin_sube_velocidad mostrar_mensaje_limite_max: printf $80,Mensaje_limite_max fin_sube_velocidad: pop r23 pop r22 pop r21 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** baja_velocidad: push r21 push r22 push r23 in r21,OCR1AL in r21,OCR1AH cpi r21,$17 breq mostrar_mensaje_limite_min clc ldi zh,high(tabla*2) ldi zl,low(tabla*2) lds r22,rr22 add zl,r22 lds r23,rr23 add zh,r23 ldi r18,2 ldi r19,0 sub zl,r18 sbc zh,r19 lpm r18,z+ lpm r19,z+ out OCR1AH,r19 out OCR1AL,r18 ldi r18,2 ldi r19,0 sub zl,r18 sbc zh,r19 dec r22 dec r22 sts rr22,r22 printf $80,espacio rjmp fin_baja_velocidad mostrar_mensaje_limite_min: printf $80,Mensaje_limite_min fin_baja_velocidad: pop r23 pop r22 pop r21 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** inicia_variables: push R16 ldi r16,0 sts flag_se_a_calibrado,r16 sts flag_inicio_faja,r16 sts flag_mostrar_datos,r16 sts envia_dat_serial,r16 sts cantid_cajas,r16 pop R16 ret ;****************************************************************************************************** ***** ;********************************************************************************* lcd_mensaje: push r16 push zh push zl rcall WriteIR lazo_muestra: lpm r16,Z+ ;Lee y muestra caracter en LCD cpi r16,0 breq fin_envia_lcd rcall WriteDR rjmp lazo_muestra fin_envia_lcd: pop zl pop zh pop r16 ret ;****************************************************************************************************** ****************** ;********************************************************************************* ;**** Subrutina: Envia una instruccion al LCD ;**** Entrada: r16 WriteIR: push R16 push r31 cbi portb,4 ;RW=0 cbi portb,5 ;E=0 cbi portd,7 ;RS=0 swap r16 ;XX54XXXX mov r31,r16 andi r31,$0f out PORTB,r31 cbi portb,4 ;RW=0 sbi portb,5 ;E=1 cbi portd,7 ;RS=0 rcall Retardo50us cbi portb,4 ;RW=0 cbi portb,5 ;E=0 cbi portd,7 ;RS=0 rcall Retardo50us swap r16 andi r16,$0F out PORTB,r16 cbi portb,4 ;RW=0 sbi portb,5 ;E=1 cbi portd,7 ;RS=0 rcall Retardo50us cbi portb,4 ;RW=0 cbi portb,5 ;E=0 cbi portd,7 ;RS=0 rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us rcall Retardo50us ;-DoEvents sbi portb,4 ;RW=1 cbi portb,5 ;E=0 cbi portd,7 ;RS=0 pop r31 pop R16 ret ;********************************************************************************* ;**** Subrutina: Envia un dato al LCD ;**** Entrada: r16 WriteDR: push R16 push R17 push r31 mov r17,r16 cbi portb,4 ;RW=0 cbi portb,5 ;E=0 sbi portd,7 ;RS=1 swap r17 mov r31,r17 andi r31,$0F out PORTB,r31 ;se envia el nibble MSB cbi portb,4 ;RW=0 sbi portb,5 ;E=1 sbi portd,7 ;RS=1 rcall Retardo50us cbi portb,4 ;RW=0 cbi portb,5 ;E=0 sbi portd,7 ;RS=1 rcall Retardo50us swap r17 andi r17,$0F out PORTB,r17 ;se envia el nibble LSB cbi portb,4 ;RW=0 sbi portb,5 ;E=1 sbi portd,7 ;RS=1 rcall Retardo50us cbi portb,4 ;RW=0 cbi portb,5 ;E=0 sbi portd,7 ;RS=1 sbi portb,4 ;RW=1 cbi portb,5 ;E=0 cbi portd,7 ;RS=0 pop r31 pop R17 pop R16 ret ;********************************************************************************* ;****************************************************************************************************** ****************** ;*** Subrutina: Configura LCD (En sus hojas técnicas se muestra ; la secuencia que se debe seguir para inicializar la pantalla LCD) ; Dar un tiempo para encender la pantalla LCD ; Configurar (Funcion Set) la pantalla para manejar r17s de 8 bits ; Configurar el control ON/OFF (desactivar el display, el cursor y el parpadeo) ; Limpiar la pantalla ; Configurar en modo Set para actualizar el contador de direcciones ; Mover el cursor a su posición inicial Configura_LCD: push R16 push R17 ldi r16,1 rcall RetardoXms ;espera 1 ms cbi portb,4 ;RW=0 ;XX54XXXX cbi portb,5 ;E=0 cbi portd,7 ;RS=0 ldi r16,$20 ;Función Set: Configuracion a 4 bits : DB7 DB6 DB5 DB4 0010xxxx swap r16 out PORTB,r16 cbi portb,4 ;RW=0 sbi portb,5 ;E=1 cbi portd,7 ;RS=0 rcall Retardo50us cbi portb,4 ;RW=0 cbi portb,5 ;E=0 cbi portd,7 ;RS=0 rcall Retardo50us rcall Retardo50us ldi r16,$28 ;Funcion Set rcall WriteIR ldi r16,$08 ;desactivar la pantalla, el cursor y el parpadeo rcall WriteIR ldi r16,$01 ;limpiar la pantalla (funcion clear) rcall WriteIR ldi r16,$06 ; El cursor avanza a la derecha cada vez que se imprime rcall WriteIR ; un caracter ldi r16,0b00001100 ;Enciende pantalla y desactivar cursor rcall WriteIR rcall char_flechas pop R17 pop R16 ret ;********************************************************************************* ;************************************************************************ Retardo50us: push R16 ldi r16,16 lazo_retardo50us: dec r16 brne lazo_retardo50us pop R16 ret ;*********************************************** ;************************************************************************ ;*** Espera milisegundos. Se asume fosc=1MHz ;*** Entrada: R16 = Numero de milisegundos ;************************************************************************ RetardoXms: push R16 push XL push XH Delayms_Lazo1: ldi XH,high(250) ldi XL,low(250) Delayms_Lazo2: sbiw XL,1 brne Delayms_Lazo2 dec R16 brne Delayms_Lazo1 pop XH pop XL pop R16 ret ;*********************************************** ;********************************************************************************* ;**** Limpia la pantalla LCD Y regresa el cursor Limpiar: push R16 ldi r16,$01 rcall WriteIR ldi r16,1 rcall RetardoXms pop R16 ret ;********************************************************************************* ;********************************************************************************* char_flechas: ldi r16,0b01001000 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01001001 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01001010 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01001011 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01001100 rcall WriteIR ldi r16,0b01011111 rcall WriteDR ldi r16,0b01001101 rcall WriteIR ldi r16,0b00001110 rcall WriteDR ldi r16,0b01001110 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ;---------------------------- ldi r16,0b01010110 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01010101 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01010100 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01010011 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01010010 rcall WriteIR ldi r16,0b01011111 rcall WriteDR ldi r16,0b01010001 rcall WriteIR ldi r16,0b00001110 rcall WriteDR ldi r16,0b01010000 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ;--------------- ldi r16,0b01011110 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01011101 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01011100 rcall WriteIR ldi r16,0b00011100 rcall WriteDR ldi r16,0b01011011 rcall WriteIR ldi r16,0b00000010 rcall WriteDR ldi r16,0b01011010 rcall WriteIR ldi r16,0b01000100 rcall WriteDR ldi r16,0b01011001 rcall WriteIR ldi r16,0b00000010 rcall WriteDR ldi r16,0b01011000 rcall WriteIR ldi r16,0b00011100 rcall WriteDR ;_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_: ldi r16,0b01100000 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100001 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100010 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100011 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100100 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100101 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100110 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01100111 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ;_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_: ldi r16,0b01101000 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01101001 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01101010 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01101011 rcall WriteIR ldi r16,0b00011111 rcall WriteDR ldi r16,0b01101100 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01101101 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01101110 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01101111 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ;_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_: ldi r16,0b01110000 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01110001 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01110010 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01110011 rcall WriteIR ldi r16,0b00011111 rcall WriteDR ldi r16,0b01110100 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01110101 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01110110 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01110111 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ;_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_:_: ldi r16,0b01111000 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01111001 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01111010 rcall WriteIR ldi r16,0b00000000 rcall WriteDR ldi r16,0b01111011 rcall WriteIR ldi r16,0b00000111 rcall WriteDR ldi r16,0b01111100 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01111101 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01111110 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ldi r16,0b01111111 rcall WriteIR ldi r16,0b00000100 rcall WriteDR ret ;********************************************************************************* *************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*** TAREA 2 - Teclado ;*************************************************************************** Tarea2: ldi R16,0b00001111 ;Puerto C: C0-C3 Filas del teclado matricial: PC0=F1 PC1=F2 PC2=F3 PC3=F4 out DDRC,R16 ; C4-C7 Colum. del teclado matricial: PC4=C1 PC5=C2 PC6=C3 PC7=C4 ldi r16,0 sts tecla,r16 teclado_lazo: DoEvents sbi portc,0 ;F1 cbi portc,1 ;F2 cbi portc,2 ;F3 cbi portc,3 ;F4 in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_1 rjmp sigue_2 tecla_1: rcall tecla_1_suelta rjmp teclado_lazo sigue_2: cpi r16,0b00100000 ;C2 breq tecla_2 rjmp sigue_3 tecla_2: rcall tecla_2_suelta rjmp teclado_lazo sigue_3: cpi r16,0b01000000 ;C3 breq tecla_3 rjmp sigue_up tecla_3: rcall tecla_3_suelta rjmp teclado_lazo sigue_up: cpi r16,0b10000000 ;C4 breq tecla_up rjmp sigue_4 tecla_up: rcall tecla_up_suelta rjmp teclado_lazo sigue_4: cbi portc,0 ;F1 sbi portc,1 ;F2 cbi portc,2 ;F3 cbi portc,3 ;F4 in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_4 rjmp sigue_5 tecla_4: rcall tecla_4_suelta rjmp teclado_lazo sigue_5: cpi r16,0b00100000 ;C2 breq tecla_5 rjmp sigue_6 tecla_5: rcall tecla_5_suelta rjmp teclado_lazo sigue_6: cpi r16,0b01000000 ;C3 breq tecla_6 rjmp sigue_down tecla_6: rcall tecla_6_suelta rjmp teclado_lazo sigue_down: cpi r16,0b10000000 ;C4 breq tecla_down rjmp sigue_7 tecla_down: rcall tecla_down_suelta rjmp teclado_lazo sigue_7: cbi portc,0 ;F1 cbi portc,1 ;F2 sbi portc,2 ;F3 cbi portc,3 ;F4 in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_7 rjmp sigue_8 tecla_7: rcall tecla_7_suelta rjmp teclado_lazo sigue_8: cpi r16,0b00100000 ;C2 breq tecla_8 rjmp sigue_9 tecla_8: rcall tecla_8_suelta rjmp teclado_lazo sigue_9: cpi r16,0b01000000 ;C3 breq tecla_9 rjmp sigue_2nd tecla_9: rcall tecla_9_suelta rjmp teclado_lazo sigue_2nd: cpi r16,0b10000000 ;C4 breq tecla_2nd rjmp sigue_clear tecla_2nd: rcall tecla_2nd_suelta rjmp teclado_lazo sigue_clear: cbi portc,0 ;F1 cbi portc,1 ;F2 cbi portc,2 ;F3 sbi portc,3 ;F4 in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_clear rjmp sigue_0 tecla_clear: rcall tecla_clear_suelta rjmp teclado_lazo sigue_0: cpi r16,0b00100000 ;C2 breq tecla_0 rjmp sigue_help tecla_0: rcall tecla_0_suelta rjmp teclado_lazo sigue_help: cpi r16,0b01000000 ;C3 breq tecla_help rjmp sigue_enter tecla_help: rcall tecla_help_suelta rjmp teclado_lazo sigue_enter: cpi r16,0b10000000 ;C4 breq tecla_enter rjmp teclado_lazo tecla_enter: rcall tecla_enter_suelta rjmp teclado_lazo tecla_1_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_1_suelta ldi r16,$11 sts tecla,r16 ret tecla_2_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00100000 ;C2 breq tecla_2_suelta ldi r16,$12 sts tecla,r16 ret tecla_3_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b01000000 ;C3 breq tecla_3_suelta ldi r16,$13 sts tecla,r16 ret tecla_up_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b10000000 ;C4 breq tecla_up_suelta ldi r16,$1A sts tecla,r16 ret tecla_4_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_4_suelta ldi r16,$14 sts tecla,r16 ret tecla_5_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00100000 ;C2 breq tecla_5_suelta ldi r16,$15 sts tecla,r16 ret tecla_6_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b01000000 ;C3 breq tecla_6_suelta ldi r16,$16 sts tecla,r16 ret tecla_down_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b10000000 ;C4 breq tecla_down_suelta ldi r16,$1B sts tecla,r16 ret tecla_7_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_7_suelta ldi r16,$17 sts tecla,r16 ret tecla_8_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00100000 ;C2 breq tecla_8_suelta ldi r16,$18 sts tecla,r16 ret tecla_9_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b01000000 ;C3 breq tecla_9_suelta ldi r16,$1f sts tecla,r16 ret tecla_2nd_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b10000000 ;C4 breq tecla_2nd_suelta ldi r16,$1d sts tecla,r16 ret tecla_clear_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00010000 ;C1 breq tecla_clear_suelta ldi r16,$1E sts tecla,r16 ret tecla_0_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b00100000 ;C2 breq tecla_0_suelta ldi r16,$10 sts tecla,r16 ret tecla_help_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b01000000 ;C3 breq tecla_help_suelta ldi r16,$1F sts tecla,r16 ret tecla_enter_suelta: DoEvents in r16,pinc andi r16,0b11110000 cpi r16,0b10000000 ;C4 breq tecla_enter_suelta ldi r16,$1D sts tecla,r16 ret ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*************************************************************************** ;*** TAREA 3 - Medicion ;*************************************************************************** Tarea3: rcall Configura_TMR1 rcall Configura_puertos rcall Configura_ADC rcall config_timer_ADC ; frecuencia de meustreo del ADC rcall config_timer_2 ; timer para calular el largo ela caja rcall config_interr_exter ;config inter externas en flacno de subida y bajada respectibamente ldi r16,0 sts datos_nuevos,r16 sts nueva_velocida,r16 sts dimensiones_nuevas,r16 Lazo_tarea3: DoEvents lds r16,flag_inicio_sensado cpi r16,10 brsh calcula_nueva_velocida rjmp Lazo_tarea3 calcula_nueva_velocida: lds r16,nueva_velocida cpi r16,10 brsh halla_veloci lds r16,datos_nuevos cpi r16,1 brsh realiza_calculos rjmp Lazo_tarea3 halla_veloci: rcall calcula_vel_faja_eprom clr r16 sts nueva_velocida,r16 rjmp Lazo_tarea3 realiza_calculos: rcall calcula_largo_guard_eprom rcall calcula_ancho_guard_eprom rcall calcula_alto_guard_eprom clr r16 sts datos_nuevos,r16 ldi r16,$ff sts dimensiones_nuevas,r16 lds r16,flag_mostrar_datos cpi r16,10 brsh muestro_datos_lcd rjmp Lazo_tarea3 muestro_datos_lcd: lds r16,vel_0 rcall convertir_a_ascii ldi r16,$e3 call WriteIR mov r16,R18 call WriteDR mov r16,R17 call WriteDR lds r16,largo rcall convertir_a_ascii ldi r16,$c6 call WriteIR mov r16,R19 call WriteDR mov r16,R18 call WriteDR ldi r16,',' call WriteDR mov r16,R17 call WriteDR lds r16,alto rcall convertir_a_ascii ldi r16,$99 call WriteIR mov r16,R19 call WriteDR mov r16,R18 call WriteDR ldi r16,',' call WriteDR mov r16,R17 call WriteDR lds r16,ancho rcall convertir_a_ascii ldi r16,$da call WriteIR mov r16,R19 call WriteDR mov r16,R18 call WriteDR ldi r16,',' call WriteDR mov r16,R17 call WriteDR ldi r16,$88 call WriteIR lds r16,alto lds r17,ancho lds r18,largo rcall mul_1byt_1byt_1byt rcall bin24_ascii mov r16,R22 call WriteDR mov r16,R21 call WriteDR mov r16,R20 call WriteDR mov r16,R19 call WriteDR ldi r16,$D1 rcall WriteIR lds r16,cantid_cajas inc r16 sts cantid_cajas,r16 rcall convertir_a_ascii mov r16,r19 rcall WriteDR mov r16,r18 rcall WriteDR mov r16,r17 rcall WriteDR nop nop nop nop rjmp Lazo_tarea3 ;****************************************************************************************************** ***** foto1_flanco_subida_bajada: push r16 lds r16,flanco_foto1 ; 1= subida 0 = bajada cpi r16,1 brlo flanco_bajada_1 ldi r16,0 sts contador,r16 out TCNT2,r16 ; contador de timer2 =0 in r16,TIMSK ori r16,0b01000000 ; abilita inter por overflow timer 2 out TIMSK,r16 ; aca inicia la cuenta del timer2 para calcular el largo in r16,TIFR ; limpia banderas de interrupcion por overflow2 ori r16,0b11000000 out TIFR,r16 ldi r16,0b00001110 ; ....1110 : INT1 falco subida foto 2 INT0 falnco bajada foto1 out MCUCR,r16 ldi r16,0 ; configura flanco de bajada sts flanco_foto1,r16 ldi R16,0b11010011 ;1:adc abilitado 1:inicio manual 0:AutoTriggering OFF 10:limpia bandera y desactiva interrupcion de fin de conversion 011:pre=8 frec conv=125K out ADCSRA, R16 rjmp fin_flanco_subida_1 flanco_bajada_1: lds r16,contador sts cuenta_largo,r16 in r16,TCNT2 ;leez contador restante de tiemr2 sts contad_restante_timer2_largo,r16 ldi r16,0 out TCNT2,r16 ;contadore timer2=0 in r16,TIMSK andi r16,0b10111111 out TIMSK,r16 ;abilita inter por overflow timer 2 in r16,MCUCR ori r16,$03 ; ......11 : INT0 falnco subida foto1 out MCUCR,r16 ldi r16,1 sts flanco_foto1,r16 sts datos_nuevos,r16 fin_flanco_subida_1: pop r16 reti ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** foto2_flanco_subida_bajada: ; en flanco de subida saca velocidad, en flanco de bajada opera dimensiones y volummen push r16 lds r16,flanco_foto2 ; 1= subida 0 = bajada cpi r16,1 brlo flanco_bajada_2 lds r16,contador sts cuenta_vel,r16 in r16,MCUCR andi r16,0b11110011 ori r16,0b00001000 ; ....1011 : INT1 falco bajada foto 2 out MCUCR,r16 in r16,TCNT2 ; lee contador restante de tiemr2 sts contad_restante_timer2_vel,r16 in r16,TIMSK ori r16,0b00000010 ;, 01....10 desab comparematch timer2 y abilita overflow timer2......... abilita int comparacion timer0 y desabilita int overflow timer0 out TIMSK,r16 ;abilita ADC ldi yh,high(adc_anch) ;ubicaion en ram para almacenar datos sts yadress,yh ldi yl,low(adc_anch) ;ubicaion en ram para almacenar datos sts yadress+1,yl ldi r16,$ff sts nueva_velocida,r16 ldi r16,0 sts flanco_foto2,r16 rjmp fin_flanco_subida_2 flanco_bajada_2: ldi r16,1 sts flanco_foto2,r16 in r16,MCUCR ori r16,$c0 ; ....11.. : INT1 falnco subida foto2 out MCUCR,r16 ldi R16,0b01010011 ;0:adc desabilitado 1:inicio manual 0:AutoTriggering OFF 10:limpia bandera y desactiva interrupcion de fin de conversion 011:pre=8 frec conv=125K out ADCSRA, R16 ldi r16,0 sts cuenta_vel,r16 sts cuenta_largo,r16 sts contador,r16 sts cantidad_datos,r16 sts contad_restante_timer2_largo,r16 sts contad_restante_timer2_vel,r16 fin_flanco_subida_2: pop r16 reti ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** fin_cuenta_timer2: push r16 lds r16,contador inc r16 sts contador,r16 ; reinicio de cuenta timer2 automatico TCNT2=0 pop r16 reti ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** Muestreo_Timer_ADC: ; lee el adc de canal 0 y canal 1 y los guarda en RAM push r16 push xh push xl ; mejorar puntero Y q se almacene n RAM sin push pop!!!!!! ldi R16,0b01000000 ;01:avcc=5v 1:ajusizq 00000:ADC0 para el canal 0 ANCHO out ADMUX,R16 rcall leeADC ; tiempo para que la conversion ese lista en ADCH y ADCL ldi xh,0 ;ubicaion en ram de ADCL ldi xl,$24 ;ubicaion en ram de ADCL ld r16,x+ ; lee y depsues pasa a ADCH lds yh,yadress lds yl,yadress+1 st y+,r16 ;ppuntero(Y): direccion donde kiero q se guarde la conversion ld r16,x st y+,r16 ldi R16,0b01000001 ;01:avcc=5v 1:ajusizq 00001:ADC1 para el canal 1 ALTO out ADMUX,R16 rcall leeADC ldi xh,0 ;ubicaion en ram de ADCL ldi xl,$24 ;ubicaion en ram de ADCL ld r16,x+ st y+,r16 ld r16,x st y+,r16 sts yadress,yh sts yadress+1,yl lds r16,cantidad_datos cpi r16,10 brlo no_apaga_timer in r16,TIMSK andi r16,0b11111101 ;, 01....10 desab comparematch timer2 y abilita overflow timer2......... abilita int comparacion timer0 y desabilita int overflow timer0 out TIMSK,r16 ldi r16,0 sts cantidad_datos,r16 rjmp fin_adc ; para q no incremente cantidad_datos no_apaga_timer: inc r16 sts cantidad_datos,r16 fin_adc: ;cantidad_datos no incrementado pop xl pop xh pop r16 reti ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** leeADC: push r16 in r16,adcsra ; ad star conversion =1 ori r16,$40 out adcsra,r16 leeADClazo: in r16,adcsra sbrc r16,6;adsc rjmp leeADClazo pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** calcula_vel_faja_eprom: push r16 push r17 push r18 push r19 push r20 push r21 lds r18,cuenta_vel clc rol r18 clr r16 clr r19 adc r19,r16 lsl r19 clc rol r18 adc r19,r16 lsl r19 clc rol r18 adc r19,r16 clr r17 ;multiplica cuenta_velx2048 ;rpt1 en r19:r18:r17 lds r20,contad_restante_timer2_vel clc rol r20 clr r16 clr r21 adc r21,r16 lsl r21 clc rol r20 adc r21,r16 lsl r21 clc rol r20 adc r21,r16 clr r22 ;multiplica contad_restante_timer2_velx8 ;rpt1 en r22:r21:r20 ;sumo los tiempos add r20,r17 adc r21,r18 adc r22,r19; tiempo total en r22:r21:20 = denominador ldi r18,byte3(distancia_fotos*100000) ldi r17,high(distancia_fotos*100000) ldi r16,low(distancia_fotos*100000) ;numerador rcall div_3byt_3byt ; divide 3 bytes ente 3 bytes entrada r18:r17:r16 / r22:r21:r20 salida : r18:r17:r16 sts vel_0,r16 pop r21 pop r20 pop r19 pop r18 pop r17 pop r16 ret ;******************************************************************************************** ;****************************************************************************************************** ***** calcula_largo_guard_eprom: push r16 lds r18,cuenta_largo clc rol r18 clr r16 clr r19 adc r19,r16 lsl r19 clc rol r18 adc r19,r16 lsl r19 clc rol r18 adc r19,r16 clr r17 ;multiplica cuenta_largox2048 ;rpt1 en r19:r18:r17 lds r20,contad_restante_timer2_largo clc rol r20 clr r16 clr r21 adc r21,r16 lsl r21 clc rol r20 adc r21,r16 lsl r21 clc rol r20 adc r21,r16 clr r22 ;multiplica contad_restante_timer2_largox8 ;rpt1 en r22:r21:r20 ;sumo los tiempos add r20,r17 adc r21,r18 adc r22,r19; tiempo total en r22:r21:20 de largo lds r16,vel_0 rcall mul_3byt_1byt ; multiplia 3 bytes por 1 byte entrada r19:r18:r17 x r16 salida: r20:r19:r18:r17 mov r16,r17 mov r17,r18 mov r18,r19 mov r19,r20 ldi r20,low(100000) ldi r21,byte2(100000) ldi r22,byte3(100000) rcall div_4byt_3byt sts largo,r16 pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** calcula_ancho_guard_eprom: push r16 push r17 push r18 push r19 push r20 push r21 push r23 lds r17,adc_anch lds r16,adc_anch+1 lds r19,adc_anch+4 lds r18,adc_anch+5 add r17,r19 adc r16,r18 lds r19,adc_anch+8 lds r18,adc_anch+9 add r17,r19 adc r16,r18 lds r19,adc_anch+12 lds r18,adc_anch+13 add r17,r19 adc r16,r18 lds r19,adc_anch+16 lds r18,adc_anch+17 add r17,r19 adc r16,r18 lds r19,adc_anch+20 lds r18,adc_anch+21 add r17,r19 adc r16,r18 lds r19,adc_anch+24 lds r18,adc_anch+25 add r17,r19 adc r16,r18 lds r19,adc_anch+28 lds r18,adc_anch+29 add r17,r19 adc r16,r18 clc ror r16 ror r17 clc ror r16 ror r17 clc ror r16 ror r17 ;entrada r18:r17 x r16 mov r18,r16 ldi r16,80 rcall mul_2byt_1byt ; rpta r19:r18:r17 ldi r16,(56) ; 56 se btiene de la formula en el documento sub r18,r16 ldi r17,(218-8) sub r17,r18 sts ancho,r17 pop r23 pop r21 pop r20 pop r19 pop r18 pop r17 pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** calcula_alto_guard_eprom: push r19 push r20 push r21 push r22 push r23 push r24 push r25 push r26 push r27 push r28 push r29 lds r17,adc_alt lds r16,adc_alt+1 lds r19,adc_alt+4 lds r18,adc_alt+5 add r17,r19 adc r16,r18 lds r19,adc_alt+8 lds r18,adc_alt+9 add r17,r19 adc r16,r18 lds r19,adc_alt+12 lds r18,adc_alt+13 add r17,r19 adc r16,r18 lds r19,adc_alt+16 lds r18,adc_alt+17 add r17,r19 adc r16,r18 lds r19,adc_alt+20 lds r18,adc_alt+21 add r17,r19 adc r16,r18 lds r19,adc_alt+24 lds r18,adc_alt+25 add r17,r19 adc r16,r18 lds r19,adc_alt+28 lds r18,adc_alt+29 add r17,r19 adc r16,r18 clc ror r16 ror r17 clc ror r16 ror r17 clc ror r16 ror r17 ;entrada r18:r17 x r16 mov r18,r16 ldi r16,77 rcall mul_2byt_1byt ; rpta r19:r18:r17 ldi r16,(54) ; 54 se btiene de la formula en el documento sub r18,r16 ldi r17,(210) sub r17,r18 sts alto,r17 pop r29 pop r28 pop r27 pop r26 pop r25 pop r24 pop r23 pop r22 pop r21 pop r20 pop r19 ret ;****************************************************************************************************** ***** ;********************************************************************************* ;Entradas: R16 ;Salidas: r19,r18,r17 convertir_a_ascii: push R16 ldi R19,0 ldi R18,0 centena: cpi R16,100 brlo decena subi R16,100 inc R19 rjmp centena decena: cpi R16,10 brlo unidad subi R16,10 inc R18 rjmp decena unidad: subi R16,-($30) mov R17,R16 subi R18,-($30) subi R19,-($30) pop R16 ret ;********************************************************************************* ;****************************************************************************************************** ***** mul_3byt_1byt: ; multiplia 3 bytes por 1 byte entrada r19:r18:r17 x r16 salida: r20:r19:r18:r17 push r16 mul r16,r17 mov r17,r0 mov r20,r1 mul r16,r18 mov r18,r0 add r18,r20 mov r20,r1 mul r16,r19 mov r19,r0 add r19,r20 mov r20,r1 ldi r16,0 adc r20,r16 pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** mul_1byt_1byt_1byt: ; nmultiplica 1 byte x 1 byte x 1byte entrada r16,r17,r18 salida r18:r17:r16 mul r17,r18 mov r18,r1 mov r17,r0 rcall mul_2byt_1byt ; rpta r19:r18:r17 mov r16,r17 mov r17,r18 mov r18,r19 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** mul_2byt_1byt: ; multiplia 2 bytes por 1 byte entrada r18:r17 x r16 salida: r19:r18:r17 push r16 mul r16,r17 mov r17,r0 mov r19,r1 mul r16,r18 mov r18,r0 add r18,r19 mov r19,r1 ldi r16,0 adc r19,r16 pop r16 ret ;****************************************************************************************************** ***** ;****************************************************************************************************** ***** div_4byt_3byt: ; divide 4 bytes entre 3 bytes entrada r19:r18:r17:r16 / r22:r21:r20 salida : r18:r17:r16 push r19 push r20 push r21 push r22 push r23 push r24 push r25 push r26 push r27 push r28 clr r28 mov r24,r20 mov r25,r21 mov r26,r22 mov r27,r23 div1: cp r23,r19 brsh div2 add r20,r24 adc r21,r25 adc r22,r26 adc r23,r27 inc r28 rjmp div1 div2: cp r22,r18 brsh div3 add r20,r24 adc r21,r25 adc r22,r26 adc r23,r27 inc r28 rjmp div2 div3: mov r16,r28 inc r16 pop r28 pop r27 pop r26 pop r25 pop r24 pop r23 pop r22 pop r21 pop r20 pop r19 ret ;****************************************************************************************************** ***** ;******************************************************************************************** div_3byt_3byt: push r19 push r20 push r21 push r22 push r24 push r25 push r26 push r27 push r28 push r29 ldi r16,0 ldi r19,1 ldi r27,0 ldi r28,0 ldi r29,0 mov r24,r20 mov r25,r21 mov r26,r22 compara: cp r18,r22 brlo resultado add r20,r24 adc r21,r25 adc r22,r26 add r27,r19 adc r28,r16 adc r29,r16 rjmp compara resultado: ;la respuesta esta en r29:r28:r27 mov r16,r27 mov r17,r28 mov r18,r29 pop r29 pop r28 pop r27 pop r26 pop r25 pop r24 pop r22 pop r21 pop r20 pop r19 ret ;******************************************************************************************** ;****************************************************************************************************** ***** Configura_TMR1: push r18 push r22 push r23 ldi r18,(1<= 3 Then MsgBox("Error en la Transmisión") End If End If End Sub '****************************************************************************************************** *********** Private Sub Buttonsalir_Click(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles Buttonsalir.Click Me.Close() End Sub '****************************************************************************************************** *********** Private Sub Buttoninicio_Click(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles Buttoninicio.Click spserial_usb = My.Computer.Ports.OpenSerialPort("COM4") spserial_usb.BaudRate = 9600 spserial_usb.DataBits = 8 spserial_usb.StopBits = 1 spserial_usb.Parity = 0 ListView1.Visible = True ListView1.View = View.Details ListView1.GridLines = True ListView1.FullRowSelect = True ListView1.HideSelection = False ListView1.MultiSelect = False 'Headings ListView1.Columns.Add("N° CAJA", 70) ListView1.Columns.Add("ALTO (cm)", 70) ListView1.Columns.Add("ANCHO (cm)", 80) ListView1.Columns.Add("LARGO (cm)", 80) ListView1.Columns.Add("VOLUMEN (cm3)", 100) For k = 0 To ListView1.Columns.Count - 1 ListView1.Columns(k).Width = -2 Next End Sub '****************************************************************************************************** *********** End Class '****************************************************************************************************** ***********