`timescale 1 ps/ 1 ps
module EM2_32bit_vlg_tst();
reg clk;
wire [31:0] memory_data;
reg req;
reg rst;
wire ack;
wire [21:0]  address_memory;
wire [356:0]  position_endmember;

EM2_32bit i1 (
	.ack(ack),
	.address_memory(address_memory),
	.clk(clk),
	.memory_data(memory_data),
	.position_endmember(position_endmember),
	.req(req),
	.rst(rst)
);

memory_EM2_32bit stage_memory (.indice(address_memory),.valor(memory_data));

initial                                                
begin
rst=1'b1;
req=1'b0;
@(posedge(clk));
@(posedge(clk));
rst=1'b0;
@(posedge(clk));
#1;
req=1'b1;
#10;
@(posedge(ack));
#10;
$stop;                                                  
end
                                                    
always                                                 
begin                                                  
#1 clk=1'b0;
#1 clk=1'b1;
end                                                    

endmodule

