module selecionador_fila
#(
	parameter WIDTH = 16,
	parameter ENDMEMBER = 21
)
(
	// Input Ports
	input clk,rst,
	input en,
	input [(WIDTH*ENDMEMBER*ENDMEMBER-1):0] matrix,
	input [4:0]sel,
	// Output Ports
	output [WIDTH*ENDMEMBER-1:0]fila
);
wire [WIDTH*ENDMEMBER-1:0] seleccionado;
reg [WIDTH*ENDMEMBER-1:0] fila_reg,fila_next;

mux5bits #(.WIDTH(WIDTH*ENDMEMBER)) mux_stage
(
	.data_in(matrix),
	.sel(sel),
	.data_out(seleccionado)
);

always@(posedge clk,posedge rst)
begin
	if (rst)
		fila_reg <= 5'h00;
	else
		fila_reg <= fila_next;
end

always@(*)
begin
	if (en)
		fila_next=seleccionado;
	else
		fila_next=fila_reg;
end

assign fila=fila_reg;

endmodule
