module counter
#(parameter top=350*350)
(
	input clk,rst,
	input rst_counter,en_counter,
	output [16:0]cont_reg,cont_next
);

reg [8:0] num1_reg,num1_next;
reg [7:0] num2_reg,num2_next;



always@(posedge clk,posedge rst)
begin
if (rst)
begin
	num1_reg <=3'b000;
	num2_reg <= 3'b000;
end
else if (en_counter)
	begin
		num1_reg <= num1_next;
		num2_reg <= num2_next;
	end
end

always@(*)
begin
if (rst_counter)
begin
	num1_next <= 9'b010000011;
	num2_next <= 8'b11101111;
end
else
begin
	num1_next <= num1_reg+1'b1;
	num2_next <= num2_reg;
	if (num1_reg==9'h1FF)
		num2_next <= num2_reg+1'b1;
	if ((num1_reg==9'b010000011)&&(num2_reg == 8'b11101111))
		begin
			num1_next <= 3'b000;
			num2_next <= 3'b000;
		end
end	
end

assign cont_reg = {num2_reg,num1_reg};
assign cont_next = {num2_next,num1_next};

endmodule
