module rand_counter
#(
	parameter top=20
)
(
input	clk,rst,
input rst_rand,en_rand,
output reg [16:0]rand_reg,rand_next,
output [4:0] counter
);

reg [4:0] counter_reg,counter_next;

always@(posedge clk,posedge rst)
begin
if (rst)
	counter_reg <= 3'b000;
else
	if(en_rand)
		counter_reg <= counter_next;
end

always@(*)
begin
	counter_next = counter_reg;
	if (rst_rand)
		begin
		counter_next = 5'd20;
		end
	else
		begin
		if (counter_reg==5'd20)
			counter_next=3'b000;
		else
			counter_next = counter_reg+1'b1;
		end
end

always@(*)
begin
	case(counter_reg)
	5'd0: rand_reg = 17'd99743;
	5'd1: rand_reg = 17'd116745;
	5'd2: rand_reg = 17'd22303;
	5'd3: rand_reg = 17'd91086;
	5'd4: rand_reg = 17'd552;
	5'd5: rand_reg = 17'd34766;
	5'd6: rand_reg = 17'd93571;
	5'd7: rand_reg = 17'd49594;
	5'd8: rand_reg = 17'd29866;
	5'd9: rand_reg = 17'd19582;
	5'd10: rand_reg = 17'd58201;
	5'd11: rand_reg = 17'd59866;
	5'd12: rand_reg = 17'd15811;
	5'd13: rand_reg = 17'd117274;
	5'd14: rand_reg = 17'd96259;
	5'd15: rand_reg = 17'd51649;
	5'd16: rand_reg = 17'd60383;
	5'd17: rand_reg = 17'd57132;
	5'd18: rand_reg = 17'd111655;
	5'd19: rand_reg = 17'd59594;
	5'd20: rand_reg = 17'd86649;
	default:rand_reg = 17'd0;
	endcase
end

always@(*)
begin
	case(counter_next)
	5'd0: rand_next = 17'd99743;
	5'd1: rand_next = 17'd116745;
	5'd2: rand_next = 17'd22303;
	5'd3: rand_next = 17'd91086;
	5'd4: rand_next = 17'd552;
	5'd5: rand_next = 17'd34766;
	5'd6: rand_next = 17'd93571;
	5'd7: rand_next = 17'd49594;
	5'd8: rand_next = 17'd29866;
	5'd9: rand_next = 17'd19582;
	5'd10: rand_next = 17'd58201;
	5'd11: rand_next = 17'd59866;
	5'd12: rand_next = 17'd15811;
	5'd13: rand_next = 17'd117274;
	5'd14: rand_next = 17'd96259;
	5'd15: rand_next = 17'd51649;
	5'd16: rand_next = 17'd60383;
	5'd17: rand_next = 17'd57132;
	5'd18: rand_next = 17'd111655;
	5'd19: rand_next = 17'd59594;
	5'd20: rand_next = 17'd86649;
	default rand_next =17'd0;
	endcase
end


assign counter=counter_reg;

endmodule
