module mux5bits

#(
	parameter WIDTH = 16
)

(
	input [WIDTH*32-1:0]data_in,
	input [4:0] sel,
	// Output Ports
	output reg [WIDTH-1:0] data_out
);

always@(*)
begin
	casez(sel)
	5'd0:data_out = data_in[(WIDTH-1):0];
	5'd1:data_out = data_in[(WIDTH*2-1):(WIDTH)];
	5'd2:data_out = data_in[(WIDTH*3-1):(WIDTH*2)];
	5'd3:data_out = data_in[(WIDTH*4-1):(WIDTH*3)];
	5'd4:data_out = data_in[(WIDTH*5-1):(WIDTH*4)];
	5'd5:data_out = data_in[(WIDTH*6-1):(WIDTH*5)];
	5'd6:data_out = data_in[(WIDTH*7-1):(WIDTH*6)];
	5'd7:data_out = data_in[(WIDTH*8-1):(WIDTH*7)];
	5'd8:data_out = data_in[(WIDTH*9-1):(WIDTH*8)];
	5'd9:data_out = data_in[(WIDTH*10-1):(WIDTH*9)];
	5'd10:data_out = data_in[(WIDTH*11-1):(WIDTH*10)];
	5'd11:data_out = data_in[(WIDTH*12-1):(WIDTH*11)];
	5'd12:data_out = data_in[(WIDTH*13-1):(WIDTH*12)];
	5'd13:data_out = data_in[(WIDTH*14-1):(WIDTH*13)];
	5'd14:data_out = data_in[(WIDTH*15-1):(WIDTH*14)];
	5'd15:data_out = data_in[(WIDTH*16-1):(WIDTH*15)];
	5'd16:data_out = data_in[(WIDTH*17-1):(WIDTH*16)];
	5'd17:data_out = data_in[(WIDTH*18-1):(WIDTH*17)];
	5'd18:data_out = data_in[(WIDTH*19-1):(WIDTH*18)];
	5'd19:data_out = data_in[(WIDTH*20-1):(WIDTH*19)];
	5'd20:data_out = data_in[(WIDTH*21-1):(WIDTH*20)];
	5'd21:data_out = data_in[(WIDTH*22-1):(WIDTH*21)];
	5'd22:data_out = data_in[(WIDTH*23-1):(WIDTH*22)];
	5'd23:data_out = data_in[(WIDTH*24-1):(WIDTH*23)];
	5'd24:data_out = data_in[(WIDTH*25-1):(WIDTH*24)];
	5'd25:data_out = data_in[(WIDTH*26-1):(WIDTH*25)];
	5'd26:data_out = data_in[(WIDTH*27-1):(WIDTH*26)];
	5'd27:data_out = data_in[(WIDTH*28-1):(WIDTH*27)];
	5'd28:data_out = data_in[(WIDTH*29-1):(WIDTH*28)];
	5'd29:data_out = data_in[(WIDTH*30-1):(WIDTH*29)];
	5'd30:data_out = data_in[(WIDTH*31-1):(WIDTH*30)];
	5'd31:data_out = data_in[(WIDTH*32-1):(WIDTH*31)];
	default: data_out = 0;
	endcase
end


endmodule
