module i_register
#(
	parameter ENDMEMBER = 21
)
(
	input clk,rst,
	input en,sync,
	output [4:0] i,
	output [4:0] i_menos
);

reg [4:0] i_reg,i_next;
reg [4:0] i_menos_reg,i_menos_next;

always@(posedge clk,posedge rst)
begin
	if (rst)
	begin
		i_reg <= 5'h00;
		i_menos_reg <= 5'h00;
	end
	else
	begin
		i_reg <= i_next;
		i_menos_reg <= i_menos_next;
	end
end

always@(*)
begin
	if (en)
		if (sync)
			i_next=ENDMEMBER-1;
		else
			if (i_reg==5'h00)
				i_next=5'h00;
			else
				i_next=i_reg-1;
	else
		i_next= i_reg;
end

always@(*)
begin
	if (en)
		if (sync)
			i_menos_next=ENDMEMBER-5'd2;
		else
			if (i_menos_reg==5'h00)
				i_menos_next=5'h00;
			else
				i_menos_next=i_menos_reg-5'd1;
	else
		i_menos_next=i_menos_reg;
end

assign i = i_reg;
assign i_menos= i_menos_reg;
//
endmodule
